tcl/target/atheros_ar9331.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # The Atheros AR9331 is a highly integrated and cost effective
   4 # IEEE 802.11n 1x1 2.4 GHz System- on-a-Chip (SoC) for wireless
   5 # local area network (WLAN) AP and router platforms.
   6 #
   7 # Notes:
   8 # - MIPS Processor ID (PRId): 0x00019374
   9 # - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache,
  10 #   operating at up to 400 MHz
  11 # - External 16-bit DDR1, DDR2, or SDRAM memory interface
  12 # - TRST is not available.
  13 # - EJTAG PrRst signal is not supported
  14 # - RESET_L pin A72 on the SoC will reset internal JTAG logic.
  15 #
  16
  17 # Pins related for debug and bootstrap:
  18 # Name          Pin             Description
  19 #   JTAG
  20 # JTAG_TCK      GPIO0, (A27)    Software configurable, default JTAG
  21 # JTAG_TDI      GPIO6, (B46)    Software configurable, default JTAG
  22 # JTAG_TDO      GPIO7, (A54)    Software configurable, default JTAG
  23 # JTAG_TMS      GPIO8, (A52)    Software configurable, default JTAG
  24 #   Reset
  25 # RESET_L       -, (A72)        Input only
  26 # SYS_RST_L     ????????        Output reset request or GPIO
  27 #   Bootstrap
  28 # MEM_TYPE[1]   GPIO28, (A74)   0 - SDRAM, 1 - DDR1 RAM, 2 - DDR2 RAM
  29 # MEM_TYPE[0]   GPIO12, (A56)
  30 # FW_DOWNLOAD   GPIO16, (A75)   Used if BOOT_FROM_SPI = 0. 0 - boot from USB
  31 #                               1 - boot from MDIO.
  32 # JTAG_MODE(JS) GPIO11, (B48)   0 - JTAG (Default); 1 - EJTAG
  33 # BOOT_FROM_SPI GPIO1, (A77)    0 - ROM boot; 1 - SPI boot
  34 # SEL_25M_40M   GPIO0, (A78)    0 - 25MHz; 1 - 40MHz
  35 #   UART
  36 # UART0_SOUT    GPIO10, (A79)
  37 # UART0_SIN     GPIO9, (B68)
  38
  39 # Per default we need to use "none" variant to be able properly "reset init"
  40 # or "reset halt" the CPU.
  41 reset_config none srst_pulls_trst
  42
  43 # For SRST based variant we still need proper timings.
  44 # For ETH part the reset should be asserted at least for 10ms
  45 # Since there is no other information let's take 100ms to be sure.
  46 adapter srst pulse_width 100
  47
  48 # according to the SoC documentation it should take at least 5ms from
  49 # reset end till bootstrap end. In the practice we need 8ms to get JTAG back
  50 # to live.
  51 adapter srst delay 8
  52
  53 if { [info exists CHIPNAME] } {
  54         set _CHIPNAME $_CHIPNAME
  55 } else {
  56         set _CHIPNAME ar9331
  57 }
  58
  59 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00000001
  60
  61 set _TARGETNAME $_CHIPNAME.cpu
  62 target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
  63
  64 # provide watchdog helper.
  65 proc disable_watchdog { } {
  66         mww 0xb8060008 0x0
  67 }
  68
  69 $_TARGETNAME configure -event halted { disable_watchdog }
  70
  71 # Since PrRst is not supported and SRST will reset complete chip
  72 # with JTAG engine, we need to reset CPU from CPU itself.
  73 $_TARGETNAME configure -event reset-assert-pre {
  74         halt
  75 }
  76
  77 $_TARGETNAME configure -event reset-assert {
  78         catch "mww 0xb806001C 0x01000000"
  79 }
  80
  81 # To be able to trigger complete chip reset, in case JTAG is blocked
  82 # or CPU not responding, we still can use this helper.
  83 proc full_reset { } {
  84         reset_config srst_only
  85         reset
  86         halt
  87         reset_config none
  88 }
  89
  90 proc disable_watchdog { } {
  91         ;# disable watchdog
  92         mww 0xb8060008 0x0
  93 }
  94
  95 $_TARGETNAME configure -event reset-end { disable_watchdog }
  96
  97 # Section with helpers which can be used by boards
  98 proc ar9331_25mhz_pll_init {} {
  99         mww 0xb8050008 0x00018004       ;# bypass PLL; AHB_POST_DIV - ratio 4
 100         mww 0xb8050004 0x00000352       ;# 34000(ns)/40ns(25MHz) = 0x352 (850)
 101         mww 0xb8050000 0x40818000       ;# Power down control for CPU PLL
 102                                         ;# OUTDIV | REFDIV | DIV_INT
 103         mww 0xb8050010 0x001003e8       ;# CPU PLL Dither FRAC Register
 104                                         ;# (disabled?)
 105         mww 0xb8050000 0x00818000       ;# Power on | OUTDIV | REFDIV | DIV_INT
 106         mww 0xb8050008 0x00008000       ;# remove bypass;
 107                                         ;# AHB_POST_DIV - ratio 2
 108 }
 109
 110 proc ar9331_ddr1_init {} {
 111         mww 0xb8000000 0x7fbc8cd0       ;# DDR_CONFIG - lots of DRAM confs
 112         mww 0xb8000004 0x9dd0e6a8       ;# DDR_CONFIG2 - more DRAM confs
 113
 114         mww 0xb8000010 0x8      ;# Forces a PRECHARGE ALL cycle
 115         mww 0xb8000008 0x133    ;# mode reg: 0x133 - default
 116         mww 0xb8000010 0x1      ;# Forces an MRS update cycl
 117         mww 0xb800000c 0x2      ;# Extended mode register value.
 118                                 ;# default 0x2 - Reset to weak driver, DLL on
 119         mww 0xb8000010 0x2      ;# Forces an EMRS update cycle
 120         mww 0xb8000010 0x8      ;# Forces a PRECHARGE ALL cycle
 121         mww 0xb8000008 0x33     ;# mode reg: remove some bit?
 122         mww 0xb8000010 0x1      ;# Forces an MRS update cycl
 123         mww 0xb8000014 0x4186   ;# enable refres: bit(14) - set refresh rate
 124         mww 0xb800001c 0x8      ;# This register is used along with DQ Lane 0,
 125                                 ;# DQ[7:0], DQS_0
 126         mww 0xb8000020 0x9      ;# This register is used along with DQ Lane 1,
 127                                 ;# DQ[15:8], DQS_1.
 128         mww 0xb8000018 0xff     ;# DDR read and capture bit mask.
 129                                 ;# Each bit represents a cycle of valid data.
 130 }
 131
 132 proc ar9331_ddr2_init {} {
 133         mww 0xb8000000 0x7fbc8cd0       ;# DDR_CONFIG - lots of DRAM confs
 134         mww 0xb8000004 0x9dd0e6a8       ;# DDR_CONFIG2 - more DRAM confs
 135
 136         mww 0xb800008c 0x00000a59
 137         mww 0xb8000010 0x00000008       ;# PRECHARGE ALL cycle
 138
 139         mww 0xb8000090 0x00000000
 140         mww 0xb8000010 0x00000010       ;# EMR2S update cycle
 141
 142         mww 0xb8000094 0x00000000
 143         mww 0xb8000010 0x00000020       ;# EMR3S update cycle
 144
 145         mww 0xb800000c 0x00000000
 146         mww 0xb8000010 0x00000002       ;# EMRS update cycle
 147
 148         mww 0xb8000008 0x00000100
 149         mww 0xb8000010 0x00000001       ;# MRS update cycle
 150
 151         mww 0xb8000010 0x00000008       ;# PRECHARGE ALL cycle
 152
 153         mww 0xb8000010 0x00000004
 154         mww 0xb8000010 0x00000004       ;# AUTO REFRESH cycle
 155
 156         mww 0xb8000008 0x00000a33
 157         mww 0xb8000010 0x00000001       ;# MRS update cycle
 158
 159         mww 0xb800000c 0x00000382
 160         mww 0xb8000010 0x00000002       ;# EMRS update cycle
 161
 162         mww 0xb800000c 0x00000402
 163         mww 0xb8000010 0x00000002       ;# EMRS update cycle
 164
 165         mww 0xb8000014 0x00004186       ;# DDR_REFRESH
 166         mww 0xb800001c 0x00000008       ;# DDR_TAP_CTRL0
 167         mww 0xb8000020 0x00000009       ;# DDR_TAP_CTRL1
 168
 169         ;# DDR read and capture bit mask.
 170         ;# Each bit represents a cycle of valid data.
 171         ;# 0xff: use 16-bit DDR
 172         mww 0xb8000018 0x000000ff
 173 }