tcl/target/c100config.tcl

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # board(-config) specific parameters file.
   4
   5 # set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
   6 proc config {label} {
   7     return [dict get [configC100] $label ]
   8 }
   9
  10 # show the value for the param. with label
  11 proc showconfig {label} {
  12     echo [format "0x%x" [dict get [configC100] $label ]]
  13 }
  14
  15 # Telo board config
  16 # when there are more then one board config
  17 # use soft links to c100board-config.tcl
  18 # so that only the right board-config gets
  19 # included (just like include/configs/board-configs.h
  20 # in u-boot.
  21 proc configC100 {} {
  22     # xtal freq. 24MHz
  23     dict set configC100 CFG_REFCLKFREQ           24000000
  24
  25     # Amba Clk 165MHz
  26     dict set configC100 CONFIG_SYS_HZ_CLOCK      165000000
  27     dict set configC100 w_amba 1
  28     dict set configC100 x_amba 1
  29     # y = amba_clk * (w+1)*(x+1)*2/xtal_clk
  30     dict set configC100 y_amba [expr {[dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ]
  31
  32     # Arm Clk 450MHz, must be a multiple of 25 MHz
  33     dict set configC100 CFG_ARM_CLOCK      450000000
  34     dict set configC100 w_arm 0
  35     dict set configC100 x_arm 1
  36     # y = arm_clk * (w+1)*(x+1)*2/xtal_clk
  37     dict set configC100 y_arm [expr {[dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ]
  38
  39
  40 }
  41
  42 # This should be called for reset init event handler
  43 proc setupTelo {} {
  44
  45     # setup GPIO used as control signals for C100
  46     setupGPIO
  47     # This will allow access to lower 8MB or NOR
  48     lowGPIO5
  49     # setup NOR size,timing,etc.
  50     setupNOR
  51     # setup internals + PLL + DDR2
  52     initC100
  53 }
  54
  55
  56 proc setupNOR {} {
  57     echo "Setting up NOR: 16MB, 16-bit wide bus, CS0"
  58     # this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()
  59     set EX_CSEN_REG         [regs EX_CSEN_REG ]
  60     set EX_CS0_SEG_REG      [regs EX_CS0_SEG_REG ]
  61     set EX_CS0_CFG_REG      [regs EX_CS0_CFG_REG ]
  62     set EX_CS0_TMG1_REG     [regs EX_CS0_TMG1_REG ]
  63     set EX_CS0_TMG2_REG     [regs EX_CS0_TMG2_REG ]
  64     set EX_CS0_TMG3_REG     [regs EX_CS0_TMG3_REG ]
  65     set EX_CLOCK_DIV_REG    [regs EX_CLOCK_DIV_REG ]
  66     set EX_MFSM_REG         [regs EX_MFSM_REG ]
  67     set EX_CSFSM_REG        [regs EX_CSFSM_REG ]
  68     set EX_WRFSM_REG        [regs EX_WRFSM_REG ]
  69     set EX_RDFSM_REG        [regs EX_RDFSM_REG ]
  70
  71     # enable Expansion Bus Clock + CS0 (NOR)
  72     mww $EX_CSEN_REG 0x3
  73     # set the address space for CS0=16MB
  74     mww $EX_CS0_SEG_REG 0x7ff
  75     # set the CS0 bus width to 16-bit
  76     mww $EX_CS0_CFG_REG 0x202
  77     # set timings to NOR
  78     mww $EX_CS0_TMG1_REG 0x03034006
  79     mww $EX_CS0_TMG2_REG 0x04040002
  80     #mww $EX_CS0_TMG3_REG
  81     # set EBUS clock 165/5=33MHz
  82     mww $EX_CLOCK_DIV_REG 0x5
  83     # everything else is OK with default
  84 }
  85
  86 proc bootNOR {} {
  87     set EXP_CS0_BASEADDR       [regs EXP_CS0_BASEADDR]
  88     set BLOCK_RESET_REG        [regs BLOCK_RESET_REG]
  89     set DDR_RST                [regs DDR_RST]
  90
  91     # put DDR controller in reset (so that it comes reset in u-boot)
  92     mmw $BLOCK_RESET_REG 0x0 $DDR_RST
  93     # setup CS0 controller for NOR
  94     setupNOR
  95     # make sure we are accessing the lower part of NOR
  96     lowGPIO5
  97     # set PC to start of NOR (at boot 0x20000000 = 0x0)
  98     reg pc $EXP_CS0_BASEADDR
  99     # run
 100     resume
 101 }
 102 proc setupGPIO {} {
 103     echo "Setting up GPIO block for Telo"
 104     # This is current setup for Telo (see sch. for details):
 105     #GPIO0 reset for FXS-FXO IC, leave as input, the IC has internal pullup
 106     #GPIO1 irq line for FXS-FXO
 107     #GPIO5 addr22 for NOR flash (access to upper 8MB)
 108     #GPIO17 reset for DECT module.
 109     #GPIO29 CS_n for NAND
 110
 111     set GPIO_OUTPUT_REG             [regs GPIO_OUTPUT_REG]
 112     set GPIO_OE_REG                 [regs GPIO_OE_REG]
 113
 114     # set GPIO29=GPIO17=1, GPIO5=0
 115     mww $GPIO_OUTPUT_REG [expr {1<<29 | 1<<17}]
 116     # enable [as output] GPIO29,GPIO17,GPIO5
 117     mww $GPIO_OE_REG [expr  {1<<29 | 1<<17 | 1<<5}]
 118 }
 119
 120 proc highGPIO5 {} {
 121     echo "GPIO5 high"
 122     set GPIO_OUTPUT_REG             [regs GPIO_OUTPUT_REG]
 123     # set GPIO5=1
 124     mmw $GPIO_OUTPUT_REG [expr {1 << 5}] 0x0
 125 }
 126
 127 proc lowGPIO5 {} {
 128     echo "GPIO5 low"
 129     set GPIO_OUTPUT_REG             [regs GPIO_OUTPUT_REG]
 130     # set GPIO5=0
 131     mmw $GPIO_OUTPUT_REG 0x0 [expr {1 << 5}]
 132 }
 133
 134 proc boardID {id} {
 135     # so far built:
 136     # 4'b1111
 137     dict set boardID 15 name "EVT1"
 138     dict set boardID 15 ddr2size 128M
 139     # dict set boardID 15 nandsize 1G
 140     # dict set boardID 15 norsize 16M
 141     # 4'b0000
 142     dict set boardID 0 name "EVT2"
 143     dict set boardID 0 ddr2size 128M
 144     # 4'b0001
 145     dict set boardID 1 name "EVT3"
 146     dict set boardID 1 ddr2size 256M
 147     # 4'b1110
 148     dict set boardID 14 name "EVT3_old"
 149     dict set boardID 14 ddr2size 128M
 150     # 4'b0010
 151     dict set boardID 2 name "EVT4"
 152     dict set boardID 2 ddr2size 256M
 153
 154     return $boardID
 155 }
 156
 157
 158 # converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect()
 159 # figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors
 160 proc ooma_board_detect {} {
 161     set GPIO_BOOTSTRAP_REG      [regs GPIO_BOOTSTRAP_REG]
 162
 163     # read the current value of the BOOTSTRAP pins
 164     set tmp [mrw $GPIO_BOOTSTRAP_REG]
 165     echo [format "GPIO_BOOTSTRAP_REG  (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
 166     # extract the GPBP bits
 167     set gpbt [expr {($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3}]
 168
 169     # display board ID
 170     echo [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt]
 171     # show it on serial console
 172     putsUART0 [format "This is %s (0x%x)\n" [dict get [boardID $gpbt] $gpbt name] $gpbt]
 173     # return the ddr2 size, used to configure DDR2 on a given board.
 174     return [dict get [boardID $gpbt] $gpbt ddr2size]
 175 }
 176
 177 proc configureDDR2regs_256M {} {
 178
 179     set DENALI_CTL_00_DATA    [regs DENALI_CTL_00_DATA]
 180     set DENALI_CTL_01_DATA    [regs DENALI_CTL_01_DATA]
 181     set DENALI_CTL_02_DATA    [regs DENALI_CTL_02_DATA]
 182     set DENALI_CTL_03_DATA    [regs DENALI_CTL_03_DATA]
 183     set DENALI_CTL_04_DATA    [regs DENALI_CTL_04_DATA]
 184     set DENALI_CTL_05_DATA    [regs DENALI_CTL_05_DATA]
 185     set DENALI_CTL_06_DATA    [regs DENALI_CTL_06_DATA]
 186     set DENALI_CTL_07_DATA    [regs DENALI_CTL_07_DATA]
 187     set DENALI_CTL_08_DATA    [regs DENALI_CTL_08_DATA]
 188     set DENALI_CTL_09_DATA    [regs DENALI_CTL_09_DATA]
 189     set DENALI_CTL_10_DATA    [regs DENALI_CTL_10_DATA]
 190     set DENALI_CTL_11_DATA    [regs DENALI_CTL_11_DATA]
 191     set DENALI_CTL_12_DATA    [regs DENALI_CTL_12_DATA]
 192     set DENALI_CTL_13_DATA    [regs DENALI_CTL_13_DATA]
 193     set DENALI_CTL_14_DATA    [regs DENALI_CTL_14_DATA]
 194     set DENALI_CTL_15_DATA    [regs DENALI_CTL_15_DATA]
 195     set DENALI_CTL_16_DATA    [regs DENALI_CTL_16_DATA]
 196     set DENALI_CTL_17_DATA    [regs DENALI_CTL_17_DATA]
 197     set DENALI_CTL_18_DATA    [regs DENALI_CTL_18_DATA]
 198     set DENALI_CTL_19_DATA    [regs DENALI_CTL_19_DATA]
 199     set DENALI_CTL_20_DATA    [regs DENALI_CTL_20_DATA]
 200
 201     set DENALI_CTL_02_VAL 0x0100000000010100
 202     set DENALI_CTL_11_VAL 0x433a32164a560a00
 203
 204     mw64bit $DENALI_CTL_00_DATA  0x0100000101010101
 205     # 01_DATA mod [40]=1, enable BA2
 206     mw64bit $DENALI_CTL_01_DATA  0x0100010100000001
 207     mw64bit $DENALI_CTL_02_DATA  $DENALI_CTL_02_VAL
 208     mw64bit $DENALI_CTL_03_DATA  0x0102020202020201
 209     mw64bit $DENALI_CTL_04_DATA  0x0000010100000001
 210     mw64bit $DENALI_CTL_05_DATA  0x0203010300010101
 211     mw64bit $DENALI_CTL_06_DATA  0x060a020200020202
 212     mw64bit $DENALI_CTL_07_DATA  0x0000000300000206
 213     mw64bit $DENALI_CTL_08_DATA  0x6400003f3f0a0209
 214     mw64bit $DENALI_CTL_09_DATA  0x1a000000001a1a1a
 215     mw64bit $DENALI_CTL_10_DATA  0x0120202020191a18
 216     # 11_DATA mod [39-32]=16,more refresh
 217     mw64bit $DENALI_CTL_11_DATA  $DENALI_CTL_11_VAL
 218     mw64bit $DENALI_CTL_12_DATA  0x0000000000000800
 219     mw64bit $DENALI_CTL_13_DATA  0x0010002000100040
 220     mw64bit $DENALI_CTL_14_DATA  0x0010004000100040
 221     mw64bit $DENALI_CTL_15_DATA  0x04f8000000000000
 222     mw64bit $DENALI_CTL_16_DATA  0x000000002cca0000
 223     mw64bit $DENALI_CTL_17_DATA  0x0000000000000000
 224     mw64bit $DENALI_CTL_18_DATA  0x0302000000000000
 225     mw64bit $DENALI_CTL_19_DATA  0x00001300c8030600
 226     mw64bit $DENALI_CTL_20_DATA  0x0000000081fe00c8
 227
 228     set wr_dqs_shift 0x40
 229     # start DDRC
 230     mw64bit $DENALI_CTL_02_DATA [expr {$DENALI_CTL_02_VAL | (1 << 32)}]
 231     # wait int_status[2] (DRAM init complete)
 232     echo -n "Waiting for DDR2 controller to init..."
 233     set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]]
 234     while { [expr {$tmp & 0x040000}] == 0 } {
 235         sleep 1
 236         set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]]
 237     }
 238     echo "done."
 239
 240     # do ddr2 training sequence
 241     # TBD (for now, if you need it, run trainDDR command)
 242 }
 243
 244 # converted from u-boot/cpu/arm1136/comcerto/bsp100.c:config_board99()
 245 # The values are computed based on Mindspeed and Nanya datasheets
 246 proc configureDDR2regs_128M {} {
 247
 248     set DENALI_CTL_00_DATA    [regs DENALI_CTL_00_DATA]
 249     set DENALI_CTL_01_DATA    [regs DENALI_CTL_01_DATA]
 250     set DENALI_CTL_02_DATA    [regs DENALI_CTL_02_DATA]
 251     set DENALI_CTL_03_DATA    [regs DENALI_CTL_03_DATA]
 252     set DENALI_CTL_04_DATA    [regs DENALI_CTL_04_DATA]
 253     set DENALI_CTL_05_DATA    [regs DENALI_CTL_05_DATA]
 254     set DENALI_CTL_06_DATA    [regs DENALI_CTL_06_DATA]
 255     set DENALI_CTL_07_DATA    [regs DENALI_CTL_07_DATA]
 256     set DENALI_CTL_08_DATA    [regs DENALI_CTL_08_DATA]
 257     set DENALI_CTL_09_DATA    [regs DENALI_CTL_09_DATA]
 258     set DENALI_CTL_10_DATA    [regs DENALI_CTL_10_DATA]
 259     set DENALI_CTL_11_DATA    [regs DENALI_CTL_11_DATA]
 260     set DENALI_CTL_12_DATA    [regs DENALI_CTL_12_DATA]
 261     set DENALI_CTL_13_DATA    [regs DENALI_CTL_13_DATA]
 262     set DENALI_CTL_14_DATA    [regs DENALI_CTL_14_DATA]
 263     set DENALI_CTL_15_DATA    [regs DENALI_CTL_15_DATA]
 264     set DENALI_CTL_16_DATA    [regs DENALI_CTL_16_DATA]
 265     set DENALI_CTL_17_DATA    [regs DENALI_CTL_17_DATA]
 266     set DENALI_CTL_18_DATA    [regs DENALI_CTL_18_DATA]
 267     set DENALI_CTL_19_DATA    [regs DENALI_CTL_19_DATA]
 268     set DENALI_CTL_20_DATA    [regs DENALI_CTL_20_DATA]
 269
 270
 271     set DENALI_CTL_02_VAL 0x0100010000010100
 272     set DENALI_CTL_11_VAL 0x433A42124A650A37
 273     # set some default values
 274     mw64bit $DENALI_CTL_00_DATA  0x0100000101010101
 275     mw64bit $DENALI_CTL_01_DATA  0x0100000100000101
 276     mw64bit $DENALI_CTL_02_DATA  $DENALI_CTL_02_VAL
 277     mw64bit $DENALI_CTL_03_DATA  0x0102020202020201
 278     mw64bit $DENALI_CTL_04_DATA  0x0201010100000201
 279     mw64bit $DENALI_CTL_05_DATA  0x0203010300010101
 280     mw64bit $DENALI_CTL_06_DATA  0x050A020200020202
 281     mw64bit $DENALI_CTL_07_DATA  0x000000030E0B0205
 282     mw64bit $DENALI_CTL_08_DATA  0x6427003F3F0A0209
 283     mw64bit $DENALI_CTL_09_DATA  0x1A00002F00001A00
 284     mw64bit $DENALI_CTL_10_DATA  0x01202020201A1A1A
 285     mw64bit $DENALI_CTL_11_DATA  $DENALI_CTL_11_VAL
 286     mw64bit $DENALI_CTL_12_DATA  0x0000080000000800
 287     mw64bit $DENALI_CTL_13_DATA  0x0010002000100040
 288     mw64bit $DENALI_CTL_14_DATA  0x0010004000100040
 289     mw64bit $DENALI_CTL_15_DATA  0x0508000000000000
 290     mw64bit $DENALI_CTL_16_DATA  0x000020472D200000
 291     mw64bit $DENALI_CTL_17_DATA  0x0000000008000000
 292     mw64bit $DENALI_CTL_18_DATA  0x0302000000000000
 293     mw64bit $DENALI_CTL_19_DATA  0x00001400C8030604
 294     mw64bit $DENALI_CTL_20_DATA  0x00000000823600C8
 295
 296     set wr_dqs_shift 0x40
 297     # start DDRC
 298     mw64bit $DENALI_CTL_02_DATA [expr {$DENALI_CTL_02_VAL | (1 << 32)}]
 299     # wait int_status[2] (DRAM init complete)
 300     echo -n "Waiting for DDR2 controller to init..."
 301     set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]]
 302     while { [expr {$tmp & 0x040000}] == 0 } {
 303         sleep 1
 304         set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]]
 305     }
 306     # This is not necessary
 307     #mw64bit $DENALI_CTL_11_DATA [expr {($DENALI_CTL_11_VAL  & ~0x00007F0000000000) | ($wr_dqs_shift << 40)} ]
 308     echo "done."
 309
 310     # do ddr2 training sequence
 311     # TBD (for now, if you need it, run trainDDR command)
 312 }
 313
 314
 315
 316 proc setupUART0 {} {
 317     # configure UART0 to 115200, 8N1
 318     set GPIO_LOCK_REG      [regs GPIO_LOCK_REG]
 319     set GPIO_IOCTRL_REG    [regs GPIO_IOCTRL_REG]
 320     set GPIO_IOCTRL_VAL    [regs GPIO_IOCTRL_VAL]
 321     set GPIO_IOCTRL_UART0  [regs GPIO_IOCTRL_UART0]
 322     set UART0_LCR                   [regs UART0_LCR]
 323     set LCR_DLAB                    [regs LCR_DLAB]
 324     set UART0_DLL                   [regs UART0_DLL]
 325     set UART0_DLH                   [regs UART0_DLH]
 326     set UART0_IIR                   [regs UART0_IIR]
 327     set UART0_IER                   [regs UART0_IER]
 328     set LCR_ONE_STOP                [regs LCR_ONE_STOP]
 329     set LCR_CHAR_LEN_8              [regs LCR_CHAR_LEN_8]
 330     set FCR_XMITRES                 [regs FCR_XMITRES]
 331     set FCR_RCVRRES                 [regs FCR_RCVRRES]
 332     set FCR_FIFOEN                  [regs FCR_FIFOEN]
 333     set IER_UUE                     [regs IER_UUE]
 334
 335     # unlock writing to IOCTRL register
 336     mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
 337     # enable UART0
 338     mmw $GPIO_IOCTRL_REG $GPIO_IOCTRL_UART0 0x0
 339     # baudrate  115200
 340     # This should really be amba_clk/(16*115200) but amba_clk=165MHz
 341     set tmp 89
 342     # Enable Divisor Latch access
 343     mmw  $UART0_LCR $LCR_DLAB 0x0
 344     # set the divisor to $tmp
 345     mww $UART0_DLL [expr {$tmp & 0xff}]
 346     mww $UART0_DLH [expr {$tmp >> 8}]
 347     # Disable Divisor Latch access
 348     mmw  $UART0_LCR 0x0 $LCR_DLAB
 349     # set the UART to 8N1
 350     mmw  $UART0_LCR [expr {$LCR_ONE_STOP | $LCR_CHAR_LEN_8} ] 0x0
 351     # reset FIFO
 352     mmw  $UART0_IIR [expr {$FCR_XMITRES  | $FCR_RCVRRES | $FCR_FIFOEN} ] 0x0
 353     #  enable FFUART
 354     mww $UART0_IER $IER_UUE
 355 }
 356
 357 proc putcUART0 {char} {
 358
 359     set UART0_LSR           [regs UART0_LSR]
 360     set UART0_THR           [regs UART0_THR]
 361     set LSR_TEMT            [regs LSR_TEMT]
 362
 363     # convert the 'char' to digit
 364     set tmp [ scan $char %c ]
 365     # /* wait for room in the tx FIFO on FFUART */
 366     while {[expr {[mrw $UART0_LSR] & $LSR_TEMT}] == 0} { sleep 1 }
 367     mww $UART0_THR $tmp
 368     if { $char == "\n" } { putcUART0 \r }
 369 }
 370
 371 proc putsUART0 {str} {
 372     set index 0
 373     set len [string length $str]
 374     while { $index < $len } {
 375         putcUART0 [string index $str $index]
 376         set index [expr {$index + 1}]
 377     }
 378 }
 379
 380
 381 proc trainDDR2 {} {
 382     set ARAM_BASEADDR   [regs ARAM_BASEADDR]
 383
 384     # you must have run 'reset init' or u-boot
 385     # load the training code to ARAM
 386     load_image ./images/ddr2train.bin $ARAM_BASEADDR bin
 387     # set PC to start of NOR (at boot 0x20000000 = 0x0)
 388     reg pc $ARAM_BASEADDR
 389     # run
 390     resume
 391 }
 392
 393 proc flashUBOOT {file} {
 394     # this will update uboot on NOR partition
 395     set EXP_CS0_BASEADDR       [regs EXP_CS0_BASEADDR]
 396
 397     # setup CS0 controller for NOR
 398     setupNOR
 399     # make sure we are accessing the lower part of NOR
 400     lowGPIO5
 401     flash probe 0
 402     echo "Erasing sectors 0-3 for uboot"
 403     putsUART0 "Erasing sectors 0-3 for uboot\n"
 404     flash erase_sector 0 0 3
 405     echo "Programming u-boot"
 406     putsUART0 "Programming u-boot..."
 407     arm11 memwrite burst enable
 408     flash write_image $file $EXP_CS0_BASEADDR
 409     arm11 memwrite burst disable
 410     putsUART0 "done.\n"
 411     putsUART0 "Rebooting, please wait!\n"
 412     reboot
 413 }