nrf51: Add UICR writing support
[openocd.git] / tcl / target / imx35.cfg
1 # imx35 config
2 #
3
4 reset_config trst_and_srst srst_gates_jtag
5 jtag_ntrst_delay 100
6
7 if { [info exists CHIPNAME] } {
8 set _CHIPNAME $CHIPNAME
9 } else {
10 set _CHIPNAME imx35
11 }
12
13 if { [info exists ENDIAN] } {
14 set _ENDIAN $ENDIAN
15 } else {
16 set _ENDIAN little
17 }
18
19 if { [info exists CPUTAPID] } {
20 set _CPUTAPID $CPUTAPID
21 } else {
22 set _CPUTAPID 0x07b3601d
23 }
24
25 if { [info exists SDMATAPID] } {
26 set _SDMATAPID $SDMATAPID
27 } else {
28 set _SDMATAPID 0x0882601d
29 }
30
31 if { [info exists ETBTAPID] } {
32 set _ETBTAPID $ETBTAPID
33 } else {
34 set _ETBTAPID 0x2b900f0f
35 }
36
37 #========================================
38
39 jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
40 jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
41
42 # No IDCODE for this TAP
43 jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0x0 -expected-id 0x0
44
45 jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
46
47 set _TARGETNAME $_CHIPNAME.cpu
48 target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
49
50 proc power_restore {} { echo "Sensed power restore. No action." }
51 proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
52
53 # trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
54 etm config $_TARGETNAME 16 normal full etb
55 etb config $_TARGETNAME $_CHIPNAME.etb

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