tcl/target/imx6.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #
   4 # Freescale i.MX6 series
   5 #
   6 # Supports 6Q 6D 6QP 6DP 6DL 6S 6SL 6SLL
   7 #
   8 # Some imx6 chips have Cortex-A7 or an Cortex-M and need special handling
   9 #
  10
  11 if { [info exists CHIPNAME] } {
  12    set  _CHIPNAME $CHIPNAME
  13 } else {
  14    set  _CHIPNAME imx6
  15 }
  16
  17 # CoreSight Debug Access Port
  18 if { [info exists DAP_TAPID] } {
  19     set _DAP_TAPID $DAP_TAPID
  20 } else {
  21     set _DAP_TAPID 0x4ba00477
  22 }
  23
  24 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
  25         -expected-id $_DAP_TAPID
  26
  27 # SDMA / no IDCODE
  28 jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
  29
  30 # System JTAG Controller
  31
  32 # List supported SJC TAPIDs from imx reference manuals:
  33 set _SJC_TAPID_6Q   0x0191c01d
  34 set _SJC_TAPID_6D   0x0191e01d
  35 set _SJC_TAPID_6QP  0x3191c01d
  36 set _SJC_TAPID_6DP  0x3191d01d
  37 set _SJC_TAPID_6DL  0x0891a01d
  38 set _SJC_TAPID_6S   0x0891b01d
  39 set _SJC_TAPID_6SL  0x0891f01d
  40 set _SJC_TAPID_6SLL 0x088c201d
  41
  42 # Allow external override of the first SJC TAPID
  43 if { [info exists SJC_TAPID] } {
  44     set _SJC_TAPID $SJC_TAPID
  45 } else {
  46     set _SJC_TAPID $_SJC_TAPID_6Q
  47 }
  48
  49 jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
  50         -ignore-version \
  51         -expected-id $_SJC_TAPID \
  52         -expected-id $_SJC_TAPID_6QP \
  53         -expected-id $_SJC_TAPID_6DP \
  54         -expected-id $_SJC_TAPID_6D \
  55         -expected-id $_SJC_TAPID_6DL \
  56         -expected-id $_SJC_TAPID_6S \
  57         -expected-id $_SJC_TAPID_6SL \
  58         -expected-id $_SJC_TAPID_6SLL
  59
  60 # GDB target: Cortex-A9, using DAP, configuring only one core
  61 # Base addresses of cores:
  62 # core 0  -  0x82150000
  63 # core 1  -  0x82152000
  64 # core 2  -  0x82154000
  65 # core 3  -  0x82156000
  66 set _TARGETNAME $_CHIPNAME.cpu.0
  67 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  68 target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
  69         -coreid 0 -dbgbase 0x82150000
  70
  71 # some TCK cycles are required to activate the DEBUG power domain
  72 jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
  73
  74 proc imx6_dbginit {target} {
  75         # General Cortex-A8/A9 debug initialisation
  76         cortex_a dbginit
  77 }
  78
  79 # Slow speed to be sure it will work
  80 adapter speed 1000
  81 $_TARGETNAME configure -event reset-start { adapter speed 1000 }
  82
  83 $_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"