tcl/target/imx8qm.cfg

   1 #
   2 # NXP i.MX8QuadMax
   3 #
   4
   5 if { [info exists CHIPNAME] } {
   6    set  _CHIPNAME $CHIPNAME
   7 } else {
   8    set  _CHIPNAME imx8qm
   9 }
  10
  11 # CoreSight Debug Access Port (DAP)
  12 if { [info exists DAP_TAPID] } {
  13     set _DAP_TAPID $DAP_TAPID
  14 } else {
  15     # TAPID is from FreeScale!
  16     set _DAP_TAPID 0x1890101d
  17 }
  18
  19 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
  20         -expected-id $_DAP_TAPID
  21
  22 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  23
  24 # AXI: Main SOC bus on AP #0
  25 target create ${_CHIPNAME}.axi mem_ap -dap ${_CHIPNAME}.dap -ap-num 0
  26
  27 # 4x Cortex-A53 on AP #6
  28 set _A53_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
  29 set _A53_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
  30
  31 cti create $_CHIPNAME.a53_cti.0 -dap $_CHIPNAME.dap \
  32             -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 0]
  33 cti create $_CHIPNAME.a53_cti.1 -dap $_CHIPNAME.dap \
  34             -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 1]
  35 cti create $_CHIPNAME.a53_cti.2 -dap $_CHIPNAME.dap \
  36             -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 2]
  37 cti create $_CHIPNAME.a53_cti.3 -dap $_CHIPNAME.dap \
  38             -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 3]
  39 target create $_CHIPNAME.a53.0 aarch64 -dap $_CHIPNAME.dap \
  40             -cti $_CHIPNAME.a53_cti.0 -dbgbase [lindex $_A53_DBGBASE 0]
  41 target create $_CHIPNAME.a53.1 aarch64 -dap $_CHIPNAME.dap \
  42             -cti $_CHIPNAME.a53_cti.1 -dbgbase [lindex $_A53_DBGBASE 1] -defer-examine
  43 target create $_CHIPNAME.a53.2 aarch64 -dap $_CHIPNAME.dap \
  44             -cti $_CHIPNAME.a53_cti.2 -dbgbase [lindex $_A53_DBGBASE 2] -defer-examine
  45 target create $_CHIPNAME.a53.3 aarch64 -dap $_CHIPNAME.dap \
  46             -cti $_CHIPNAME.a53_cti.3 -dbgbase [lindex $_A53_DBGBASE 3] -defer-examine
  47
  48 # 2x Cortex-A72 on AP #6
  49 set _A72_DBGBASE {0x80210000 0x80310000}
  50 set _A72_CTIBASE {0x80220000 0x80220000}
  51
  52 cti create $_CHIPNAME.a72_cti.0 -dap $_CHIPNAME.dap \
  53             -ap-num 6 -baseaddr [lindex $_A72_CTIBASE 0]
  54 cti create $_CHIPNAME.a72_cti.1 -dap $_CHIPNAME.dap \
  55             -ap-num 6 -baseaddr [lindex $_A72_CTIBASE 1]
  56 target create $_CHIPNAME.a72.0 aarch64 -dap $_CHIPNAME.dap \
  57             -cti $_CHIPNAME.a72_cti.0 -dbgbase [lindex $_A72_DBGBASE 0] -defer-examine
  58 target create $_CHIPNAME.a72.1 aarch64 -dap $_CHIPNAME.dap \
  59             -cti $_CHIPNAME.a72_cti.1 -dbgbase [lindex $_A72_DBGBASE 1] -defer-examine
  60
  61 # All Cortex-A in SMP
  62 target smp \
  63         $_CHIPNAME.a53.0 \
  64         $_CHIPNAME.a53.1 \
  65         $_CHIPNAME.a53.2 \
  66         $_CHIPNAME.a53.3 \
  67         $_CHIPNAME.a72.0 \
  68         $_CHIPNAME.a72.1
  69
  70 # SCU: Cortex-M4 core
  71 # always running imx SC firmware
  72 target create ${_CHIPNAME}.scu cortex_m -dap ${_CHIPNAME}.dap -ap-num 1
  73
  74 # AHB from SCU perspective
  75 target create ${_CHIPNAME}.scu_ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 4
  76
  77 # Cortex-M4 M4_0 core on AP #2 (default off)
  78 target create ${_CHIPNAME}.m4_0 cortex_m -dap ${_CHIPNAME}.dap -ap-num 2 \
  79         -defer-examine
  80
  81 # Cortex-M4 M4_1 core on AP #3 (default off)
  82 target create ${_CHIPNAME}.m4_1 cortex_m -dap ${_CHIPNAME}.dap -ap-num 3 \
  83         -defer-examine
  84
  85 # Debug APB bus
  86 target create ${_CHIPNAME}.apb mem_ap -dap ${_CHIPNAME}.dap -ap-num 6
  87
  88 # Default target is boot core a53.0
  89 targets $_CHIPNAME.a53.0