tcl/target/kl25z_hla.cfg

   1 # MKL25Z128VLK4
   2 # FreeScale Cortex-M0plus with 128kB Flash and 16kB Local On-Chip SRAM
   3
   4 if { [info exists CHIPNAME] == 0 } {
   5    set _CHIPNAME kl25z
   6 }
   7
   8 if { [info exists CPUTAPID] == 0 } {
   9    set _CPUTAPID 0x0BC11477
  10 }
  11
  12 if { [info exists WORKAREASIZE] == 0 } {
  13    set _WORKAREASIZE 0x3000
  14 }
  15
  16 if { [info exists TRANSPORT] == 0 } {
  17    set _TRANSPORT hla_swd
  18 }
  19
  20 transport select $_TRANSPORT
  21
  22 hla newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
  23
  24 set _TARGETNAME $_CHIPNAME.cpu
  25 target create $_TARGETNAME hla_target -chain-position $_TARGETNAME
  26
  27 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  28
  29 flash bank pflash kinetis 0x00000000 0x20000 0 4 $_TARGETNAME
  30
  31 proc kl25z_enable_pll {} {
  32         echo "KL25Z: Enabling PLL"
  33         # SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
  34         mww     0x40048044      0x00020000
  35         # /* Switch to FEI Mode */
  36         # MCG->C1 = (uint8_t)0x06U;
  37         mwb 0x40064000  0x06
  38         # MCG->C2 = (uint8_t)0x00U;
  39         mwb 0x40064001  0x00
  40         # /* MCG->C4: DMX32=0,DRST_DRS=1 */
  41         # MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
  42         mwb 0x40064003  0x37
  43         #OSC0->CR = (uint8_t)0x80U;
  44         mwb 0x40065000  0x80
  45         # MCG->C5 = (uint8_t)0x00U;
  46         mwb 0x40064004  0x00
  47         # MCG->C6 = (uint8_t)0x00U;
  48         mwb 0x40064005  0x00
  49         sleep 100
  50 }
  51
  52 $_TARGETNAME configure -event reset-init {
  53         kl25z_enable_pll
  54 }
  55