tcl/target/lpc11uxx.cfg

   1 #
   2 # NXP lpc11uxx family
   3
   4 source [find target/swj-dp.tcl]
   5
   6 if { [info exists CHIPNAME] } {
   7         set _CHIPNAME $CHIPNAME
   8 } else {
   9         set _CHIPNAME lpc11uxx
  10 }
  11
  12 if { [info exists ENDIAN] } {
  13         set _ENDIAN $ENDIAN
  14 } else {
  15         set _ENDIAN little
  16 }
  17
  18 # Work-area is a space in RAM used for flash programming
  19 # By default use 6kB
  20 if { [info exists WORKAREASIZE] } {
  21    set _WORKAREASIZE $WORKAREASIZE
  22 } else {
  23    set _WORKAREASIZE 0x1800
  24 }
  25
  26 if { [info exists CPUTAPID] } {
  27         set _CPUTAPID $CPUTAPID
  28 } else {
  29         set _CPUTAPID 0x00000000
  30 }
  31
  32 # delays on reset lines
  33 adapter_nsrst_delay 100
  34 #jtag_ntrst_delay 100
  35
  36 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  37
  38 set _TARGETNAME $_CHIPNAME.cpu
  39 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  40
  41 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  42
  43 #set _FLASHNAME $_CHIPNAME.flash
  44 #flash bank $_FLASHNAME lpc2000 0 0 0 0 $_TARGETNAME
  45
  46 if {![using_hla]} {
  47    # if srst is not fitted use SYSRESETREQ to
  48    # perform a soft reset
  49    cortex_m reset_config sysresetreq
  50 }