tcl/target/lpc1756.cfg

   1 # !!!!!!!!!!!!
   2 # ! UNTESTED !
   3 # !!!!!!!!!!!!
   4
   5 # NXP LPC1756 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM,
   6 set CHIPNAME lpc1756
   7 set CPUTAPID 0x4ba00477
   8 set CPURAMSIZE 0x8000
   9 set CPUROMSIZE 0x40000
  10
  11 # After reset the chip is clocked by the ~4MHz internal RC oscillator.
  12 # When board-specific code (reset-init handler or device firmware)
  13 # configures another oscillator and/or PLL0, set CCLK to match; if
  14 # you don't, then flash erase and write operations may misbehave.
  15 # (The ROM code doing those updates cares about core clock speed...)
  16 #
  17 # CCLK is the core clock frequency in KHz
  18 set CCLK 4000
  19
  20 #Include the main configuration file.
  21 source [find target/lpc17xx.cfg];