tcl/target/lpc1768.cfg

   1 # NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, clocked with 4MHz internal RC oscillator
   2
   3 if { [info exists CHIPNAME] } {
   4         set  _CHIPNAME $CHIPNAME
   5 } else {
   6         set  _CHIPNAME lpc1768
   7 }
   8
   9 if { [info exists ENDIAN] } {
  10         set  _ENDIAN $ENDIAN
  11 } else {
  12         set  _ENDIAN little
  13 }
  14
  15 if { [info exists CPUTAPID ] } {
  16         set _CPUTAPID $CPUTAPID
  17 } else {
  18         set _CPUTAPID 0x4ba00477
  19 }
  20
  21 #delays on reset lines
  22 jtag_nsrst_delay 200
  23 jtag_ntrst_delay 200
  24
  25 # LPC2000 & LPC1700 -> SRST causes TRST
  26 reset_config trst_and_srst srst_pulls_trst
  27
  28 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  29
  30 set _TARGETNAME $_CHIPNAME.cpu
  31 target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
  32
  33 # LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
  34 $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0
  35
  36 $_TARGETNAME configure -event reset-init {
  37         # Force target into ARM state
  38         armv4_5 core_state arm
  39         #do not remap 0x0000-0x0020 to anything but the flash
  40 #       mwb 0xE01FC040 0x01
  41         mwb 0xE000ED08 0x00
  42 }
  43
  44 # LPC1768 has 512kB of user-available FLASH (bootloader is located in separate dedicated region).
  45 # flash bank lpc1700 <base> <size> 0 0 <target#> <variant> <cclk> [calc_checksum]
  46
  47 flash bank lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 12000 calc_checksum
  48
  49 # 4MHz / 6 = 666kHz, so use 500
  50 jtag_khz 500