68b33c4bb55ec15c360f719d61f1ede1e9fe9bb8
[openocd.git] / tcl / target / lpc1768.cfg
1 # NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
2
3 # LPC17xx chips support both JTAG and SWD transports.
4 # Adapt based on what transport is active.
5 source [find target/swj-dp.tcl]
6
7 if { [info exists CHIPNAME] } {
8 set _CHIPNAME $CHIPNAME
9 } else {
10 set _CHIPNAME lpc1768
11 }
12
13 # After reset the chip is clocked by the ~4MHz internal RC oscillator.
14 # When board-specific code (reset-init handler or device firmware)
15 # configures another oscillator and/or PLL0, set CCLK to match; if
16 # you don't, then flash erase and write operations may misbehave.
17 # (The ROM code doing those updates cares about core clock speed...)
18 #
19 # CCLK is the core clock frequency in KHz
20 if { [info exists CCLK ] } {
21 set _CCLK $CCLK
22 } else {
23 set _CCLK 4000
24 }
25 if { [info exists CPUTAPID ] } {
26 set _CPUTAPID $CPUTAPID
27 } else {
28 set _CPUTAPID 0x4ba00477
29 }
30
31 #delays on reset lines
32 adapter_nsrst_delay 200
33 jtag_ntrst_delay 200
34
35 # LPC2000 & LPC1700 -> SRST causes TRST
36 reset_config srst_pulls_trst
37
38 #jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
39 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
40
41 set _TARGETNAME $_CHIPNAME.cpu
42 target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
43
44 # LPC1768 has 32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
45 # and 32K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000).
46 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000
47
48 # LPC1768 has 512kB of flash memory, managed by ROM code (including a
49 # boot loader which verifies the flash exception table's checksum).
50 # flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
51 set _FLASHNAME $_CHIPNAME.flash
52 flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \
53 lpc1700 $_CCLK calc_checksum
54
55 # Run with *real slow* clock by default since the
56 # boot rom could have been playing with the PLL, so
57 # we have no idea what clock the target is running at.
58 jtag_khz 10
59
60 $_TARGETNAME configure -event reset-init {
61 # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
62 # "User Flash Mode" where interrupt vectors are _not_ remapped,
63 # and reside in flash instead).
64 #
65 # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
66 # Bit Symbol Value Description Reset
67 # value
68 # 0 MAP Memory map control. 0
69 # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
70 # 1 User mode. The on-chip Flash memory is mapped to address 0.
71 # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
72 #
73 # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
74
75 mww 0x400FC040 0x01
76 }

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