tcl/target/lpc1768.cfg

   1 # NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
   2
   3 # LPC17xx chips support both JTAG and SWD transports.
   4 # Adapt based on what transport is active.
   5 source [find target/swj-dp.tcl]
   6
   7 if { [info exists CHIPNAME] } {
   8         set _CHIPNAME $CHIPNAME
   9 } else {
  10         set _CHIPNAME lpc1768
  11 }
  12
  13 # After reset the chip is clocked by the ~4MHz internal RC oscillator.
  14 # When board-specific code (reset-init handler or device firmware)
  15 # configures another oscillator and/or PLL0, set CCLK to match; if
  16 # you don't, then flash erase and write operations may misbehave.
  17 # (The ROM code doing those updates cares about core clock speed...)
  18 #
  19 # CCLK is the core clock frequency in KHz
  20 if { [info exists CCLK] } {
  21         set _CCLK $CCLK
  22 } else {
  23         set _CCLK 4000
  24 }
  25
  26 if { [info exists CPUTAPID] } {
  27         set _CPUTAPID $CPUTAPID
  28 } else {
  29         set _CPUTAPID 0x4ba00477
  30 }
  31
  32 if { [info exists CPURAMSIZE] } {
  33   set _CPURAMSIZE $CPURAMSIZE
  34 } else {
  35   set _CPURAMSIZE 0x8000
  36 }
  37
  38 if { [info exists CPUROMSIZE] } {
  39   set _CPUROMSIZE $CPUROMSIZE
  40 } else {
  41   set _CPUROMSIZE 0x80000
  42 }
  43
  44 #delays on reset lines
  45 adapter_nsrst_delay 200
  46 jtag_ntrst_delay 200
  47
  48 #jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  49 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  50
  51 set _TARGETNAME $_CHIPNAME.cpu
  52 target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
  53
  54 # LPC1768 has 32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
  55 # and 32K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000).
  56 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
  57
  58 # LPC1768 has 512kB of flash memory, managed by ROM code (including a
  59 # boot loader which verifies the flash exception table's checksum).
  60 # flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
  61 set _FLASHNAME $_CHIPNAME.flash
  62 flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \
  63         lpc1700 $_CCLK calc_checksum
  64
  65 # Run with *real slow* clock by default since the
  66 # boot rom could have been playing with the PLL, so
  67 # we have no idea what clock the target is running at.
  68 adapter_khz 10
  69
  70 $_TARGETNAME configure -event reset-init {
  71         # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
  72         # "User Flash Mode" where interrupt vectors are _not_ remapped,
  73         # and reside in flash instead).
  74         #
  75         # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
  76         # Bit Symbol Value Description Reset
  77         # value
  78         # 0 MAP Memory map control. 0
  79         # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
  80         # 1 User mode. The on-chip Flash memory is mapped to address 0.
  81         # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
  82         #
  83         # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
  84
  85         mww 0x400FC040 0x01
  86 }