tcl/target/lpc1768.cfg

   1 # NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
   2
   3 if { [info exists CHIPNAME] } {
   4         set  _CHIPNAME $CHIPNAME
   5 } else {
   6         set  _CHIPNAME lpc1768
   7 }
   8
   9 # After reset the chip is clocked by the ~4MHz internal RC oscillator.
  10 # When board-specific code (reset-init handler or device firmware)
  11 # configures another oscillator and/or PLL0, set CCLK to match; if
  12 # you don't, then flash erase and write operations may misbehave.
  13 # (The ROM code doing those updates cares about core clock speed...)
  14 #
  15 # CCLK is the core clock frequency in KHz
  16 if { [info exists CCLK ] } {
  17         set _CCLK $CCLK
  18 } else {
  19         set _CCLK 4000
  20 }
  21 if { [info exists CPUTAPID ] } {
  22         set _CPUTAPID $CPUTAPID
  23 } else {
  24         set _CPUTAPID 0x4ba00477
  25 }
  26
  27 #delays on reset lines
  28 adapter_nsrst_delay 200
  29 jtag_ntrst_delay 200
  30
  31 # LPC2000 & LPC1700 -> SRST causes TRST
  32 reset_config srst_pulls_trst
  33
  34 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  35
  36 set _TARGETNAME $_CHIPNAME.cpu
  37 target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
  38
  39 # LPC1768 has 32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
  40 # and 32K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000).
  41 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000
  42
  43 # LPC1768 has 512kB of flash memory, managed by ROM code (including a
  44 # boot loader which verifies the flash exception table's checksum).
  45 # flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
  46 set _FLASHNAME $_CHIPNAME.flash
  47 flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \
  48         lpc1700 $_CCLK calc_checksum
  49
  50 # JTAG clock should be CCLK/6 (unless using adaptive clocking)
  51 # CCLK is 4 MHz after reset, and until board-specific code (like
  52 # a reset-init handler) speeds it up.
  53 jtag_rclk [ expr 4000 / 6 ]
  54 $_TARGETNAME configure -event reset-start { jtag_rclk [ expr 4000 / 6]  }
  55
  56
  57 $_TARGETNAME configure -event reset-init {
  58         # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
  59         # "User Flash Mode" where interrupt vectors are _not_ remapped,
  60         # and reside in flash instead).
  61         #
  62         # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
  63         # Bit Symbol Value Description Reset
  64         # value
  65         # 0 MAP Memory map control. 0
  66         # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
  67         # 1 User mode. The on-chip Flash memory is mapped to address 0.
  68         # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
  69         #
  70         # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
  71
  72         mww 0x400FC040 0x01
  73 }