tcl/target/lpc1xxx.cfg

   1 # Main file for NXP LPC1xxx/LPC40xx series Cortex-M0/0+/3/4F parts
   2 #
   3 # !!!!!!
   4 #
   5 # This file should not be included directly, rather by the lpc11xx.cfg,
   6 # lpc13xx.cfg, lpc17xx.cfg, etc. which set the needed variables to the
   7 # appropriate values.
   8 #
   9 # !!!!!!
  10
  11 # LPC8xx chips support only SWD transport.
  12 # LPC11xx chips support only SWD transport.
  13 # LPC12xx chips support only SWD transport.
  14 # LPC11Uxx chips support only SWD transports.
  15 # LPC13xx chips support only SWD transports.
  16 # LPC17xx chips support both JTAG and SWD transports.
  17 # LPC40xx chips support both JTAG and SWD transports.
  18 # Adapt based on what transport is active.
  19 source [find target/swj-dp.tcl]
  20
  21 if { [info exists CHIPNAME] } {
  22         set _CHIPNAME $CHIPNAME
  23 } else {
  24         error "CHIPNAME not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
  25 }
  26
  27 if { [info exists CHIPSERIES] } {
  28         # Validate chip series is supported
  29         if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700"  && $CHIPSERIES != "lpc4000" } {
  30                 error "Unsupported LPC1xxx chip series specified."
  31         }
  32         set _CHIPSERIES $CHIPSERIES
  33 } else {
  34         error "CHIPSERIES not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
  35 }
  36
  37 # After reset, the chip is clocked by an internal RC oscillator.
  38 # When board-specific code (reset-init handler or device firmware)
  39 # configures another oscillator and/or PLL0, set CCLK to match; if
  40 # you don't, then flash erase and write operations may misbehave.
  41 # (The ROM code doing those updates cares about core clock speed...)
  42 # CCLK is the core clock frequency in KHz
  43 if { [info exists CCLK] } {
  44         # Allow user override
  45         set _CCLK $CCLK
  46 } else {
  47         # LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one(except for LPC177x/8x,LPC407x/8x)
  48         if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
  49                 set _CCLK 12000
  50         } elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
  51                 set _CCLK 4000
  52         }
  53 }
  54
  55 if { [info exists CPUTAPID] } {
  56         # Allow user override
  57         set _CPUTAPID $CPUTAPID
  58 } else {
  59         # LPC8xx/LPC11xx/LPC12xx use a Cortex M0/M0+ core, LPC13xx/LPC17xx use a Cortex M3 core,LPC40xx use a Cortex-M4F core.
  60         if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } {
  61                 set _CPUTAPID 0x0bb11477
  62         } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
  63                 if { [using_jtag] } {
  64                         set _CPUTAPID 0x4ba00477
  65                 } {
  66                         set _CPUTAPID 0x2ba01477
  67                 }
  68         }
  69 }
  70
  71 if { [info exists WORKAREASIZE] } {
  72         set _WORKAREASIZE $WORKAREASIZE
  73 } else {
  74         error "WORKAREASIZE is not set. The $CHIPNAME part is available in several Flash and RAM size configurations. Please set WORKAREASIZE."
  75 }
  76
  77 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  78
  79 set _TARGETNAME $_CHIPNAME.cpu
  80 target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
  81
  82 # The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
  83 # The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
  84 # The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
  85 # The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
  86 # The LPC17xx devices have 8/16/32/64kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
  87 # The LPC40xx devices have 16/32/64kB of SRAM in the ARMv7-ME "Code" area (at 0x10000000)
  88 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
  89
  90 # The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000)
  91 # The LPC12xx devies have 32/48/64/80/96/128kB of flash memory (at 0x00000000)
  92 # The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000)
  93 # The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000)
  94 # The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000)
  95 # The LPC40xx devies have 64/128/256/512kB of flash memory (at 0x00000000)
  96 #
  97 # All are compatible with the "lpc1700" variant of the LPC2000 flash driver
  98 # (same cmd51 destination boundary alignment, and all three support 256 byte
  99 # transfers).
 100 #
 101 # flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
 102 set _FLASHNAME $_CHIPNAME.flash
 103 flash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \
 104         auto $_CCLK calc_checksum
 105
 106 if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
 107         # Do not remap 0x0000-0x0200 to anything but the flash (i.e. select
 108         # "User Flash Mode" where interrupt vectors are _not_ remapped,
 109         # and reside in flash instead).
 110         #
 111         # Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
 112         # Bit Symbol Value Description
 113         # 1:0 MAP          System memory remap
 114         #            0x0   Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
 115         #            0x1   User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
 116         #            0x2   User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
 117         # 31:2 -     -     Reserved.
 118         $_TARGETNAME configure -event reset-init {
 119                 mww 0x40048000 0x02
 120         }
 121 } elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
 122         # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
 123         # "User Flash Mode" where interrupt vectors are _not_ remapped,
 124         # and reside in flash instead).
 125         #
 126         # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
 127         # Bit Symbol Value Description Reset
 128         # value
 129         # 0 MAP Memory map control. 0
 130         # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
 131         # 1 User mode. The on-chip Flash memory is mapped to address 0.
 132         # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
 133         #
 134         # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
 135         $_TARGETNAME configure -event reset-init {
 136                 mww 0x400FC040 0x01
 137         }
 138 }
 139
 140 # Run with *real slow* clock by default since the
 141 # boot rom could have been playing with the PLL, so
 142 # we have no idea what clock the target is running at.
 143 adapter_khz 10
 144
 145 # delays on reset lines
 146 adapter_nsrst_delay 200
 147 if {[using_jtag]} {
 148  jtag_ntrst_delay 200
 149 }
 150
 151 # LPC8xx (Cortex M0+ core) support SYSRESETREQ
 152 # LPC11xx/LPC12xx (Cortex M0 core) support SYSRESETREQ
 153 # LPC13xx/LPC17xx (Cortex M3 core) support SYSRESETREQ
 154 # LPC40xx (Cortex M4F core) support SYSRESETREQ
 155 if {![using_hla]} {
 156     # if srst is not fitted use SYSRESETREQ to
 157     # perform a soft reset
 158     cortex_m reset_config sysresetreq
 159 }