tcl/target/lpc1xxx.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # Main file for NXP LPC1xxx/LPC40xx series Cortex-M0/0+/3/4F parts
   4 #
   5 # !!!!!!
   6 #
   7 # This file should not be included directly, rather by the lpc11xx.cfg,
   8 # lpc13xx.cfg, lpc17xx.cfg, etc. which set the needed variables to the
   9 # appropriate values.
  10 #
  11 # !!!!!!
  12
  13 # LPC8xx chips support only SWD transport.
  14 # LPC11xx chips support only SWD transport.
  15 # LPC12xx chips support only SWD transport.
  16 # LPC11Uxx chips support only SWD transports.
  17 # LPC13xx chips support only SWD transports.
  18 # LPC17xx chips support both JTAG and SWD transports.
  19 # LPC40xx chips support both JTAG and SWD transports.
  20 # Adapt based on what transport is active.
  21 source [find target/swj-dp.tcl]
  22
  23 if { [info exists CHIPNAME] } {
  24         set _CHIPNAME $CHIPNAME
  25 } else {
  26         error "CHIPNAME not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
  27 }
  28
  29 if { [info exists CHIPSERIES] } {
  30         # Validate chip series is supported
  31         if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700"  && $CHIPSERIES != "lpc4000" } {
  32                 error "Unsupported LPC1xxx chip series specified."
  33         }
  34         set _CHIPSERIES $CHIPSERIES
  35 } else {
  36         error "CHIPSERIES not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
  37 }
  38
  39 # After reset, the chip is clocked by an internal RC oscillator.
  40 # When board-specific code (reset-init handler or device firmware)
  41 # configures another oscillator and/or PLL0, set CCLK to match; if
  42 # you don't, then flash erase and write operations may misbehave.
  43 # (The ROM code doing those updates cares about core clock speed...)
  44 # CCLK is the core clock frequency in KHz
  45 if { [info exists CCLK] } {
  46         # Allow user override
  47         set _CCLK $CCLK
  48 } else {
  49         # LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one(except for LPC177x/8x,LPC407x/8x)
  50         if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
  51                 set _CCLK 12000
  52         } elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
  53                 set _CCLK 4000
  54         }
  55 }
  56
  57 if { [info exists CPUTAPID] } {
  58         # Allow user override
  59         set _CPUTAPID $CPUTAPID
  60 } else {
  61         # LPC8xx/LPC11xx/LPC12xx use a Cortex-M0/M0+ core, LPC13xx/LPC17xx use a Cortex-M3 core, LPC40xx use a Cortex-M4F core.
  62         if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } {
  63                 set _CPUTAPID 0x0bb11477
  64         } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
  65                 if { [using_jtag] } {
  66                         set _CPUTAPID 0x4ba00477
  67                 } {
  68                         set _CPUTAPID 0x2ba01477
  69                 }
  70         }
  71 }
  72
  73 if { [info exists WORKAREASIZE] } {
  74         set _WORKAREASIZE $WORKAREASIZE
  75 } else {
  76         error "WORKAREASIZE is not set. The $CHIPNAME part is available in several Flash and RAM size configurations. Please set WORKAREASIZE."
  77 }
  78
  79 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  80 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  81
  82 set _TARGETNAME $_CHIPNAME.cpu
  83 target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
  84
  85 # The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
  86 # The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
  87 # The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
  88 # The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
  89 # The LPC17xx devices have 8/16/32/64kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
  90 # The LPC40xx devices have 16/32/64kB of SRAM in the ARMv7-ME "Code" area (at 0x10000000)
  91 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
  92
  93 # The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000)
  94 # The LPC12xx devies have 32/48/64/80/96/128kB of flash memory (at 0x00000000)
  95 # The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000)
  96 # The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000)
  97 # The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000)
  98 # The LPC40xx devies have 64/128/256/512kB of flash memory (at 0x00000000)
  99 #
 100 # All are compatible with the "lpc1700" variant of the LPC2000 flash driver
 101 # (same cmd51 destination boundary alignment, and all three support 256 byte
 102 # transfers).
 103 #
 104 # flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum] [iap entry]
 105 set _IAP_ENTRY 0
 106 if { [info exists IAP_ENTRY] } {
 107         set _IAP_ENTRY $IAP_ENTRY
 108 }
 109 set _FLASHNAME $_CHIPNAME.flash
 110 flash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \
 111         auto $_CCLK calc_checksum $_IAP_ENTRY
 112
 113 if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
 114         # Do not remap 0x0000-0x0200 to anything but the flash (i.e. select
 115         # "User Flash Mode" where interrupt vectors are _not_ remapped,
 116         # and reside in flash instead).
 117         #
 118         # Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
 119         # Bit Symbol Value Description
 120         # 1:0 MAP          System memory remap
 121         #            0x0   Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
 122         #            0x1   User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
 123         #            0x2   User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
 124         # 31:2 -     -     Reserved.
 125         $_TARGETNAME configure -event reset-init {
 126                 mww 0x40048000 0x02
 127         }
 128 } elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
 129         # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
 130         # "User Flash Mode" where interrupt vectors are _not_ remapped,
 131         # and reside in flash instead).
 132         #
 133         # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
 134         # Bit Symbol Value Description Reset
 135         # value
 136         # 0 MAP Memory map control. 0
 137         # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
 138         # 1 User mode. The on-chip Flash memory is mapped to address 0.
 139         # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
 140         #
 141         # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
 142         $_TARGETNAME configure -event reset-init {
 143                 mww 0x400FC040 0x01
 144         }
 145 }
 146
 147 # Run with *real slow* clock by default since the
 148 # boot rom could have been playing with the PLL, so
 149 # we have no idea what clock the target is running at.
 150 adapter speed 10
 151
 152 # delays on reset lines
 153 adapter srst delay 200
 154 if {[using_jtag]} {
 155  jtag_ntrst_delay 200
 156 }
 157
 158 # LPC8xx (Cortex-M0+ core) support SYSRESETREQ
 159 # LPC11xx/LPC12xx (Cortex-M0 core) support SYSRESETREQ
 160 # LPC13xx/LPC17xx (Cortex-M3 core) support SYSRESETREQ
 161 # LPC40xx (Cortex-M4F core) support SYSRESETREQ
 162 if {![using_hla]} {
 163     # if srst is not fitted use SYSRESETREQ to
 164     # perform a soft reset
 165     cortex_m reset_config sysresetreq
 166 }