tcl/target/lpc4350.cfg

   1
   2 adapter_khz 500
   3
   4 if { [info exists CHIPNAME] } {
   5         set _CHIPNAME $CHIPNAME
   6 } else {
   7         set _CHIPNAME lpc4350
   8 }
   9
  10 #
  11 # M4 JTAG mode TAP
  12 #
  13 if { [info exists M4_JTAG_TAPID] } {
  14         set _M4_JTAG_TAPID $M4_JTAG_TAPID
  15 } else {
  16         set _M4_JTAG_TAPID 0x4ba00477
  17 }
  18
  19 #
  20 # M4 SWD mode TAP
  21 #
  22 if { [info exists M4_SWD_TAPID] } {
  23         set _M4_SWD_TAPID $M4_SWD_TAPID
  24 } else {
  25         set _M4_SWD_TAPID 0x2ba01477
  26 }
  27
  28 #
  29 # M0 TAP
  30 #
  31 if { [info exists M0_JTAG_TAPID] } {
  32         set _M0_JTAG_TAPID $M0_JTAG_TAPID
  33 } else {
  34         set _M0_JTAG_TAPID 0x0ba01477
  35 }
  36
  37 jtag newtap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
  38                                 -expected-id $_M4_JTAG_TAPID
  39
  40 jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
  41                                 -expected-id $_M0_JTAG_TAPID
  42
  43 target create $_CHIPNAME.m4 cortex_m3 -chain-position $_CHIPNAME.m4
  44 target create $_CHIPNAME.m0 cortex_m3 -chain-position $_CHIPNAME.m0
  45
  46 # on this CPU we should use VECTRESET to perform a soft reset and
  47 # manually reset the periphery
  48 # SRST or SYSRESETREQ disable the debug interface for the time of
  49 # the reset and will not fit our requirements for a consistent debug
  50 # session
  51 cortex_m3 reset_config vectreset