tcl/target/lpc8nxx.cfg

   1 # NXP LPC8Nxx NHS31xx Cortex-M0+ with 8kB SRAM
   2 # Copyright (C) 2018 by Jean-Christian de Rivaz
   3 # Based on NXP proposal https://community.nxp.com/message/1011149
   4 # Many thanks to Dries Moors from NXP support.
   5 # SWD only transport
   6
   7 source [find target/swj-dp.tcl]
   8 source [find mem_helper.tcl]
   9
  10 if { [info exists CHIPNAME] } {
  11         set  _CHIPNAME $CHIPNAME
  12 } else {
  13         set  _CHIPNAME lpc8nxx
  14 }
  15
  16 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id 0
  17 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  18
  19 set _TARGETNAME $_CHIPNAME.cpu
  20 target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
  21 if {![using_hla]} {
  22         # If srst is not fitted use SYSRESETREQ to  perform a soft reset
  23         cortex_m reset_config sysresetreq
  24 }
  25 adapter srst delay 100
  26
  27 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x1ff0 -work-area-backup 0
  28
  29 flash bank $_CHIPNAME.flash lpc2000 0x0 0x7800 0 0 $_TARGETNAME lpc800 500
  30
  31 echo "*********************************************************************************"
  32 echo "*         !!!!! IMPORTANT NOTICE FOR LPC8Nxx and NHS31xx CHIPS !!!!!"
  33 echo "* When this IC is in power-off or peep power down mode, the SWD HW block is also"
  34 echo "* unpowered. These modes can be entered by firmware. The default firmware image"
  35 echo "* (flashed in production) makes use of this. Best is to avoid these power modes"
  36 echo "* during development, and only later add them when the functionality is complete."
  37 echo "* Hardware reset or NFC field are the only ways to connect in case the SWD is"
  38 echo "* powered off. OpenOCD can do a hardware reset if you wire the adapter SRST"
  39 echo "* signal to the chip RESETN pin and add the following in your configuration:"
  40 echo "*     reset_config srst_only; flash init; catch init; reset"
  41 echo "* But if the actual firmware immediately set the power down mode after reset,"
  42 echo "* OpenOCD might be not fast enough to halt the CPU before the SWD lost power. In"
  43 echo "* that case the only solution is to apply a NFC field to keep the SWD powered."
  44 echo "*********************************************************************************"
  45
  46 # Using soft-reset 'reset_config none' is strongly discouraged.
  47 # RESETN sets the system clock to 500 kHz. Unlike soft-reset does not.
  48 # Set the system clock to 500 kHz before reset to simulate the functionality of hw reset.
  49 #
  50 proc set_sysclk_500khz {} {
  51         set SYSCLKCTRL 0x40048020
  52         set SYSCLKUEN 0x40048024
  53         mww $SYSCLKUEN 0
  54         mmw $SYSCLKCTRL 0x8 0xe
  55         mww $SYSCLKUEN 1
  56         echo "Notice: sysclock set to 500kHz."
  57 }
  58
  59 # Do not remap the ARM interrupt vectors to anything but the beginning of the flash.
  60 # Table System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
  61 # Bit Symbol  Value   Description
  62 # 0   map         -   interrupt vector remap. 0 after boot.
  63 #                 0   interrupt vector reside in Flash
  64 #                 1   interrupt vector reside in SRAM
  65 # 5:1 offset      -   system memory remap offset. 00000b after boot.
  66 #            00000b   interrupt vectors in flash or remapped to SRAM but no offset
  67 #            00001b -
  68 #            00111b   interrupt vectors offset in flash or SRAM to 1K word segment
  69 #            01000b -
  70 #            11111b   interrupt vectors offset in flash to 1K word segment 8 to 31
  71 # 31:6                reserved
  72 #
  73 proc set_no_remap {} {
  74         mww 0x40048000 0x00
  75         echo "Notice: interrupt vector set to no remap."
  76 }
  77
  78 $_TARGETNAME configure -event reset-init {
  79         set_sysclk_500khz
  80         set_no_remap
  81 }