tcl/target/omap2420.cfg

   1 # Texas Instruments OMAP 2420
   2 #       http://www.ti.com/omap
   3
   4 if { [info exists CHIPNAME] } {
   5    set  _CHIPNAME $CHIPNAME
   6 } else {
   7    set  _CHIPNAME omap2420
   8 }
   9
  10 # NOTE: likes slowish clock on reset (1.5 MBit/s or less) or use RCLK
  11 reset_config srst_nogate
  12
  13 # Subsidiary TAP:  ARM7TDMIr4 plus imaging ... must add via ICEpick (addr 6).
  14 jtag newtap $_CHIPNAME iva -irlen 4 -disable
  15
  16 # Subsidiary TAP: C55x DSP ... must add via ICEpick (addr 2).
  17 jtag newtap $_CHIPNAME dsp -irlen 38 -disable
  18
  19 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
  20 if { [info exists ETB_TAPID ] } {
  21    set _ETB_TAPID $ETB_TAPID
  22 } else {
  23    set _ETB_TAPID 0x2b900f0f
  24 }
  25 jtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETB_TAPID
  26
  27 # Subsidiary TAP: ARM1136jf-s with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
  28 if { [info exists CPU_TAPID ] } {
  29    set _CPU_TAPID $CPU_TAPID
  30 } else {
  31    set _CPU_TAPID 0x07b3602f
  32 }
  33 jtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID
  34
  35 # Primary TAP: ICEpick-B (JTAG route controller) and boundary scan
  36 if { [info exists JRC_TAPID ] } {
  37    set _JRC_TAPID $JRC_TAPID
  38 } else {
  39    set _JRC_TAPID 0x01ce4801
  40 }
  41 jtag newtap $_CHIPNAME jrc -irlen 2 -expected-id $_JRC_TAPID
  42
  43 # GDB target:  the ARM.
  44 set _TARGETNAME $_CHIPNAME.arm
  45 target create $_TARGETNAME arm11 -chain-position $_TARGETNAME
  46
  47 # scratch:  framebuffer, may be initially unavailable in some chips
  48 $_TARGETNAME configure -work-area-phys 0x40210000
  49 $_TARGETNAME configure -work-area-size 0x00081000
  50 $_TARGETNAME configure -work-area-backup 0
  51
  52 # trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
  53 etm config $_TARGETNAME 16 normal full etb
  54 etb config $_TARGETNAME $_CHIPNAME.etb