tcl/target/omapl138.cfg

   1 #
   2 # Texas Instruments DaVinci family: OMAPL138
   3 #
   4 if { [info exists CHIPNAME] } {
   5    set _CHIPNAME $CHIPNAME
   6 } else {
   7    set _CHIPNAME omapl138
   8 }
   9
  10 source [find target/icepick.cfg]
  11
  12 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
  13 if { [info exists ETB_TAPID] } {
  14    set _ETB_TAPID $ETB_TAPID
  15 } else {
  16    set _ETB_TAPID 0x2b900f0f
  17 }
  18 jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID -disable
  19 jtag configure $_CHIPNAME.etb -event tap-enable \
  20         "icepick_c_tapenable $_CHIPNAME.jrc 3"
  21
  22 # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
  23 if { [info exists CPU_TAPID] } {
  24    set _CPU_TAPID $CPU_TAPID
  25 } else {
  26    set _CPU_TAPID 0x07926001
  27 }
  28 jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID -disable
  29 jtag configure $_CHIPNAME.arm -event tap-enable \
  30         "icepick_c_tapenable $_CHIPNAME.jrc 2"
  31
  32 # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
  33 if { [info exists JRC_TAPID] } {
  34    set _JRC_TAPID $JRC_TAPID
  35 } else {
  36    set _JRC_TAPID 0x0b7d102f
  37 }
  38 jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
  39
  40 jtag configure $_CHIPNAME.jrc -event setup \
  41         "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
  42
  43 ################
  44 # GDB target:  the ARM, using SRAM1 for scratch.  SRAM0 (also 8K)
  45 # and the ETB memory (4K) are other options, while trace is unused.
  46 # Little-endian; use the OpenOCD default.
  47 set _TARGETNAME $_CHIPNAME.arm
  48
  49 target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
  50 $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000
  51
  52 # be absolutely certain the JTAG clock will work with the worst-case
  53 # CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
  54 # on the PLL and starts using it.  OK to speed up after clock setup.
  55 jtag_rclk 1500
  56 $_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
  57
  58 arm7_9 fast_memory_access enable
  59 arm7_9 dcc_downloads enable
  60
  61 # trace setup
  62 etm config $_TARGETNAME 16 normal full etb
  63 etb config $_TARGETNAME $_CHIPNAME.etb
  64
  65 gdb_breakpoint_override hard
  66 arm7_9 dbgrq enable