tcl/target/pic32mx.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 if { [info exists CHIPNAME] } {
   4    set _CHIPNAME $CHIPNAME
   5 } else {
   6    set _CHIPNAME pic32mx
   7 }
   8
   9 if { [info exists ENDIAN] } {
  10    set _ENDIAN $ENDIAN
  11 } else {
  12    set _ENDIAN little
  13 }
  14
  15 if { [info exists CPUTAPID] } {
  16    set _CPUTAPID $CPUTAPID
  17 } else {
  18    set _CPUTAPID 0x30938053
  19 }
  20
  21 # default working area is 16384
  22 if { [info exists WORKAREASIZE] } {
  23    set _WORKAREASIZE $WORKAREASIZE
  24 } else {
  25    set _WORKAREASIZE 0x4000
  26 }
  27
  28 adapter srst delay 100
  29 jtag_ntrst_delay 100
  30
  31 #jtag scan chain
  32 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
  33 jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
  34
  35 set _TARGETNAME $_CHIPNAME.cpu
  36 target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
  37
  38 #
  39 # At reset the pic32mx does not allow code execution from RAM
  40 # we have to setup the BMX registers to allow this.
  41 # One limitation is that we loose the first 2k of RAM.
  42 #
  43
  44 global _PIC32MX_DATASIZE
  45 global _WORKAREASIZE
  46 set _PIC32MX_DATASIZE 0x800
  47 set _PIC32MX_PROGSIZE [expr {$_WORKAREASIZE - $_PIC32MX_DATASIZE}]
  48
  49 $_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size $_PIC32MX_PROGSIZE -work-area-backup 0
  50 $_TARGETNAME configure -event reset-init {
  51         #
  52         # from reset the pic32 cannot execute code in ram - enable ram execution
  53         # minimum offset from start of ram is 2k
  54         #
  55         global _PIC32MX_DATASIZE
  56         global _WORKAREASIZE
  57
  58         # BMXCON        set 0 wait state option by clearing BMXWSDRM bit, bit 6
  59         mww 0xbf882000 0x001f0000
  60         # BMXDKPBA: 2k kernel data @ 0xa0000000
  61         mww 0xbf882010 $_PIC32MX_DATASIZE
  62         # BMXDUDBA: 14k kernel program @ 0xa0000800 - (BMXDUDBA - BMXDKPBA)
  63         mww 0xbf882020 $_WORKAREASIZE
  64         # BMXDUPBA: 0k user program - (BMXDUPBA - BMXDUDBA)
  65         mww 0xbf882030 $_WORKAREASIZE
  66
  67         #
  68         # Set system clock to 8Mhz if the default clock configuration is set
  69         #
  70
  71         # SYSKEY register, make sure OSCCON is locked
  72         mww 0xbf80f230 0x0
  73         # SYSKEY register, write unlock sequence
  74         mww 0xbf80f230 0xaa996655
  75         mww 0xbf80f230 0x556699aa
  76         # OSCCON register + 4, clear OSCCON FRCDIV bits: 24, 25 and 26, divided by 1
  77         mww 0xbf80f004 0x07000000
  78         # SYSKEY register, relock OSCCON
  79         mww 0xbf80f230 0x0
  80 }
  81
  82 set _FLASHNAME $_CHIPNAME.flash0
  83 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
  84 # add virtual banks for kseg0 and kseg1
  85 flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
  86 flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
  87
  88 set _FLASHNAME $_CHIPNAME.flash1
  89 flash bank $_FLASHNAME pic32mx 0x1d000000 0 0 0 $_TARGETNAME
  90 # add virtual banks for kseg0 and kseg1
  91 flash bank vbank2 virtual 0xbd000000 0 0 0 $_TARGETNAME $_FLASHNAME
  92 flash bank vbank3 virtual 0x9d000000 0 0 0 $_TARGETNAME $_FLASHNAME