tcl/target/psoc4.cfg

   1 # script for Cypress PSoC 41xx/42xx family
   2
   3 #
   4 # PSoC 4 devices support SWD transports only.
   5 #
   6 source [find target/swj-dp.tcl]
   7
   8 if { [info exists CHIPNAME] } {
   9    set _CHIPNAME $CHIPNAME
  10 } else {
  11    set _CHIPNAME psoc4
  12 }
  13
  14 # Work-area is a space in RAM used for flash programming
  15 # By default use 4kB
  16 if { [info exists WORKAREASIZE] } {
  17    set _WORKAREASIZE $WORKAREASIZE
  18 } else {
  19    set _WORKAREASIZE 0x1000
  20 }
  21
  22 if { [info exists CPUTAPID] } {
  23    set _CPUTAPID $CPUTAPID
  24 } else {
  25    set _CPUTAPID 0x0bb11477
  26 }
  27
  28 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  29
  30 set _TARGETNAME $_CHIPNAME.cpu
  31 target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
  32
  33 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  34
  35 set _FLASHNAME $_CHIPNAME.flash
  36 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
  37
  38 adapter_khz 1500
  39
  40 # Reset, bloody PSoC 4 reset
  41 #
  42 # 1) XRES (nSRST) resets also SWD DP so SWD line reset and DP reinit is needed.
  43 # High level adapter stops working after SRST and needs OpenOCD restart.
  44 # If your hw does not use SRST for other circuits, use sysresetreq instead
  45 #
  46 # 2) PSoC 4 executes initialization code from system ROM after reset.
  47 # This code subsequently jumps to user flash reset vector address.
  48 # Unfortunately the system ROM code is protected from reading and debugging.
  49 # Protection breaks vector catch VC_CORERESET used for "reset halt" by cortex_m.
  50 #
  51 # Cypress uses TEST_MODE flag to loop CPU in system ROM before executing code
  52 # from user flash. Programming specifications states that TEST_MODE flag must be
  53 # set in time frame 400 usec delayed about 1 msec from reset.
  54 #
  55 # OpenOCD have no standard way how to set TEST_MODE in specified time frame.
  56 # TEST_MODE flag is set before reset instead. It worked for tested chips
  57 # despite it is not guaranteed by specification.
  58 #
  59 # 3) SWD cannot be connected during system initialization after reset.
  60 # This might be a reason for unconnecting ST-Link v2 when deasserting reset.
  61 # As a workaround arp_reset deassert is not called for hla
  62
  63 if {![using_hla]} {
  64    # if srst is not fitted use SYSRESETREQ to
  65    # perform a soft reset
  66    cortex_m reset_config sysresetreq
  67 }
  68
  69 proc ocd_process_reset_inner { MODE } {
  70         if { 0 != [string compare psoc4.cpu [target names]] } {
  71                 return -code error "PSoC 4 reset can handle only one psoc4.cpu target";
  72         }
  73         set t psoc4.cpu
  74
  75         # If this target must be halted...
  76         set halt -1
  77         if { 0 == [string compare $MODE halt] } {
  78                 set halt 1
  79         }
  80         if { 0 == [string compare $MODE init] } {
  81                 set halt 1;
  82         }
  83         if { 0 == [string compare $MODE run ] } {
  84                 set halt 0;
  85         }
  86         if { $halt < 0 } {
  87                 return -code error "Invalid mode: $MODE, must be one of: halt, init, or run";
  88         }
  89
  90         #$t invoke-event reset-start
  91         $t invoke-event reset-assert-pre
  92
  93         set TEST_MODE 0x40030014
  94         if { $halt == 1 } {
  95                 mww $TEST_MODE 0x80000000
  96         } else {
  97                 mww $TEST_MODE 0
  98         }
  99
 100         $t arp_reset assert 0
 101         $t invoke-event reset-assert-post
 102         $t invoke-event reset-deassert-pre
 103         if {![using_hla]} {     # workaround ST-Link v2 fails and forcing reconnect
 104                 $t arp_reset deassert 0
 105         }
 106         $t invoke-event reset-deassert-post
 107
 108         # Pass 1 - Now wait for any halt (requested as part of reset
 109         # assert/deassert) to happen.  Ideally it takes effect without
 110         # first executing any instructions.
 111         if { $halt } {
 112                 # Now PSoC CPU should loop in system ROM
 113                 $t arp_waitstate running 200
 114                 $t arp_halt
 115
 116                 # Catch, but ignore any errors.
 117                 catch { $t arp_waitstate halted 1000 }
 118
 119                 # Did we succeed?
 120                 set s [$t curstate]
 121
 122                 if { 0 != [string compare $s "halted" ] } {
 123                         return -code error [format "TARGET: %s - Not halted" $t]
 124                 }
 125
 126                 # Check if PSoC CPU is stopped in system ROM
 127                 set pc [ocd_reg pc]
 128                 regsub {pc[^:]*: } $pc "" pc
 129                 if { $pc < 0x10000000 || $pc > 0x1000ffff } {
 130                         return -code error [format "TARGET: %s - Not halted in system ROM, use 'reset_config none'" $t]
 131                 }
 132
 133                 # Set registers to reset vector values
 134                 mem2array value 32 0 2
 135                 reg pc [expr $value(1) & 0xfffffffe ]
 136                 reg msp $value(0)
 137
 138                 mww $TEST_MODE 0
 139         }
 140
 141         #Pass 2 - if needed "init"
 142         if { 0 == [string compare init $MODE] } {
 143                 set err [catch "$t arp_waitstate halted 5000"]
 144
 145                 # Did it halt?
 146                 if { $err == 0 } {
 147                         $t invoke-event reset-init
 148                 }
 149         }
 150
 151         $t invoke-event reset-end
 152 }