tcl/target/qualcomm_qca4531.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # The QCA4531 is a two stream (2x2) 802.11b/g/n single-band programmable
   4 # Wi-Fi System-on-Chip (SoC) for the Internet of Things (IoT).
   5 #
   6 # Product page:
   7 # https://www.qualcomm.com/products/qca4531
   8 #
   9 # Notes:
  10 # - MIPS Processor ID (PRId): 0x00019374
  11 # - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache,
  12 #   operating at up to 650 MHz
  13 # - External 16-bit DDR1, operating at up to 200 MHz, DDR2 operating at up
  14 #   to 300 MHz
  15 # - TRST is not available.
  16 # - EJTAG PrRst signal is not supported
  17 # - RESET_L pin B56 on the SoC will reset internal JTAG logic.
  18 #
  19 # Pins related for debug and bootstrap:
  20 # Name          Pin             Description
  21 #   JTAG
  22 # JTAG_TCK      GPIO0, (A27)    Software configurable, default JTAG
  23 # JTAG_TDI      GPIO1, (B23)    Software configurable, default JTAG
  24 # JTAG_TDO      GPIO2, (A28)    Software configurable, default JTAG
  25 # JTAG_TMS      GPIO3, (A29)    Software configurable, default JTAG
  26 #   Reset
  27 # RESET_L       -, (B56)        Input only
  28 # SYS_RST_L     GPIO17, (A79)   Output reset request or GPIO
  29 #   Bootstrap
  30 # JTAG_MODE     GPIO16, (A78)   0 - JTAG (Default); 1 - EJTAG
  31 # DDR_SELECT    GPIO10, (A57)   0 - DDR2; 1 - DDR1
  32 #   UART
  33 # UART0_SOUT    GPIO10, (A57)
  34 # UART0_SIN     GPIO9, (B49)
  35
  36 # Per default we need to use "none" variant to be able properly "reset init"
  37 # or "reset halt" the CPU.
  38 reset_config none srst_pulls_trst
  39
  40 # For SRST based variant we still need proper timings.
  41 # For ETH part the reset should be asserted at least for 10ms
  42 # Since there is no other information let's take 100ms to be sure.
  43 adapter srst pulse_width 100
  44
  45 # according to the SoC documentation it should take at least 5ms from
  46 # reset end till bootstrap end. In the practice we need 8ms to get JTAG back
  47 # to live.
  48 adapter srst delay 8
  49
  50 if { [info exists CHIPNAME] } {
  51         set _CHIPNAME $_CHIPNAME
  52 } else {
  53         set _CHIPNAME qca4531
  54 }
  55
  56 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00000001
  57
  58 set _TARGETNAME $_CHIPNAME.cpu
  59 target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
  60
  61 # provide watchdog helper.
  62 proc disable_watchdog { } {
  63         mww 0xb8060008 0x0
  64 }
  65
  66 $_TARGETNAME configure -event halted { disable_watchdog }
  67
  68 # Since PrRst is not supported and SRST will reset complete chip
  69 # with JTAG engine, we need to reset CPU from CPU itself.
  70 $_TARGETNAME configure -event reset-assert-pre {
  71         halt
  72 }
  73
  74 $_TARGETNAME configure -event reset-assert {
  75         catch "mww 0xb806001C 0x01000000"
  76 }
  77
  78 # To be able to trigger complete chip reset, in case JTAG is blocked
  79 # or CPU not responding, we still can use this helper.
  80 proc full_reset { } {
  81         reset_config srst_only
  82         reset
  83         halt
  84         reset_config none
  85 }
  86
  87 # Section with helpers which can be used by boards
  88 proc qca4531_ddr2_550_550_init {} {
  89         # Clear reset flags for different SoC components
  90         mww 0xb806001c 0xfeceffff
  91         mww 0xb806001c 0xeeceffff
  92         mww 0xb806001c 0xe6ceffff
  93
  94         # PMU configurations
  95         # Internal Switcher
  96         mww 0xb8116c40 0x633c8176
  97         # Increase the DDR voltage
  98         mww 0xb8116c44 0x10200000
  99         # XTAL Configurations
 100         mww 0xb81162c0 0x4b962100
 101         mww 0xb81162c4 0x480
 102         mww 0xb81162c8 0x04000144
 103         # Recommended PLL configurations
 104         mww 0xb81161c4 0x54086000
 105         mww 0xb8116244 0x54086000
 106
 107         # PLL init
 108         mww 0xb8050008 0x0131001c
 109         mww 0xb8050000 0x40001580
 110         mww 0xb8050004 0x40015800
 111         mww 0xb8050008 0x0131001c
 112         mww 0xb8050000 0x00001580
 113         mww 0xb8050004 0x00015800
 114         mww 0xb8050008 0x01310000
 115         mww 0xb8050044 0x781003ff
 116         mww 0xb8050048 0x003c103f
 117
 118         # DDR2 init
 119         mww 0xb8000108 0x401f0042
 120         mww 0xb80000b8 0x0000166d
 121         mww 0xb8000000 0xcfaaf33b
 122         mww 0xb800015c 0x0000000f
 123         mww 0xb8000004 0xa272efa8
 124         mww 0xb8000018 0x0000ffff
 125         mww 0xb80000c4 0x74444444
 126         mww 0xb80000c8 0x00000444
 127         mww 0xb8000004 0xa210ee28
 128         mww 0xb8000004 0xa2b2e1a8
 129         mww 0xb8000010 0x8
 130         mww 0xb80000bc 0x0
 131         mww 0xb8000010 0x10
 132         mww 0xb80000c0 0x0
 133         mww 0xb8000010 0x40
 134         mww 0xb800000c 0x2
 135         mww 0xb8000010 0x2
 136         mww 0xb8000008 0xb43
 137         mww 0xb8000010 0x1
 138         mww 0xb8000010 0x8
 139         mww 0xb8000010 0x4
 140         mww 0xb8000010 0x4
 141         mww 0xb8000008 0xa43
 142         mww 0xb8000010 0x1
 143         mww 0xb800000c 0x382
 144         mww 0xb8000010 0x2
 145         mww 0xb800000c 0x402
 146         mww 0xb8000010 0x2
 147         mww 0xb8000014 0x40be
 148         mww 0xb800001C 0x20
 149         mww 0xb8000020 0x20
 150         mww 0xb80000cc 0xfffff
 151
 152         # UART GPIO programming
 153         mww 0xb8040000 0xff30b
 154         mww 0xb8040044 0x908
 155         mww 0xb8040034 0x160000
 156 }