tcl/target/sim3x.cfg

   1 #
   2 # Silicon Laboratories SiM3x Cortex-M3
   3 #
   4
   5 # SiM3x devices support both JTAG and SWD transports.
   6 source [find target/swj-dp.tcl]
   7
   8 if { [info exists CHIPNAME] } {
   9    set _CHIPNAME $CHIPNAME
  10 } else {
  11    set _CHIPNAME SiM3x
  12 }
  13
  14 if { [info exists CPUTAPID] } {
  15    set _CPUTAPID $CPUTAPID
  16 } else {
  17    set _CPUTAPID 0x4ba00477
  18 }
  19
  20 if { [info exists CPURAMSIZE] } {
  21   set _CPURAMSIZE $CPURAMSIZE
  22 } else {
  23 # Minimum size of RAM in the Silicon Labs product matrix (8KB)
  24         set _CPURAMSIZE 0x2000
  25 }
  26
  27 if { [info exists CPUROMSIZE] } {
  28   set _CPUROMSIZE $CPUROMSIZE
  29 } else {
  30 # Minimum size of FLASH in the Silicon Labs product matrix (32KB)
  31         set _CPUROMSIZE 0x8000
  32 }
  33
  34 if { [info exists WORKAREASIZE] } {
  35    set _WORKAREASIZE $WORKAREASIZE
  36 } else {
  37    set _WORKAREASIZE $_CPURAMSIZE
  38 }
  39
  40 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  41 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  42
  43 set _TARGETNAME $_CHIPNAME.cpu
  44 target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
  45
  46 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
  47
  48 set _FLASHNAME $_CHIPNAME.flash
  49 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
  50
  51 adapter speed 1000
  52
  53 adapter srst delay 100
  54 if {[using_jtag]} {
  55  jtag_ntrst_delay 100
  56 }