tcl/target/snps_hsdk.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #  Copyright (C) 2019,2020 Synopsys, Inc.
   4 #  Anton Kolesov <anton.kolesov@synopsys.com>
   5 #  Didin Evgeniy <didin@synopsys.com>
   6
   7 #
   8 # HS Development Kit SoC.
   9 #
  10 # Contains quad-core ARC HS38.
  11 #
  12
  13 source [find cpu/arc/hs.tcl]
  14
  15 set _coreid 0
  16 set _dbgbase [expr {$_coreid << 13}]
  17
  18 # CHIPNAME will be used to choose core family (600, 700 or EM). As far as
  19 # OpenOCD is concerned EM and HS are identical.
  20 set _CHIPNAME arc-em
  21
  22 # OpenOCD discovers JTAG TAPs in reverse order.
  23
  24 # ARC HS38 core 4
  25 set _TARGETNAME $_CHIPNAME.cpu4
  26 jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x200c24b1
  27
  28 target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
  29 $_TARGETNAME configure -coreid $_coreid
  30 $_TARGETNAME configure -dbgbase $_dbgbase
  31 # Flush L2$.
  32 $_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME"
  33 set _coreid [expr {$_coreid + 1}]
  34 set _dbgbase [expr {$_coreid << 13}]
  35
  36 arc_hs_init_regs
  37
  38 # Enable L2 cache support for core 4.
  39 $_TARGETNAME arc cache l2 auto 1
  40
  41 # ARC HS38 core 3
  42 set _TARGETNAME $_CHIPNAME.cpu3
  43 jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x200824b1
  44
  45 target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
  46 $_TARGETNAME configure -coreid $_coreid
  47 $_TARGETNAME configure -dbgbase $_dbgbase
  48 $_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
  49 set _coreid [expr {$_coreid + 1}]
  50 set _dbgbase [expr {$_coreid << 13}]
  51
  52 arc_hs_init_regs
  53
  54 # Enable L2 cache support for core 3.
  55 $_TARGETNAME arc cache l2 auto 1
  56
  57 # ARC HS38 core 2
  58 set _TARGETNAME $_CHIPNAME.cpu2
  59 jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1
  60
  61 target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
  62 $_TARGETNAME configure -coreid $_coreid
  63 $_TARGETNAME configure -dbgbase $_dbgbase
  64 $_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
  65 set _coreid [expr {$_coreid + 1}]
  66 set _dbgbase [expr {$_coreid << 13}]
  67
  68 arc_hs_init_regs
  69
  70 # Enable L2 cache support for core 2.
  71 $_TARGETNAME arc cache l2 auto 1
  72
  73 # ARC HS38 core 1
  74 set _TARGETNAME $_CHIPNAME.cpu1
  75 jtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x200024b1
  76
  77 target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
  78 $_TARGETNAME configure -coreid $_coreid
  79 $_TARGETNAME configure -dbgbase $_dbgbase
  80 $_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
  81 set _coreid [expr {$_coreid + 1}]
  82 set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
  83 arc_hs_init_regs
  84
  85 # Enable L2 cache support for core 1.
  86 $_TARGETNAME arc cache l2 auto 1