tcl/target/stellaris.cfg

   1 # TI/Luminary Stellaris LM3S chip family
   2
   3 if { [info exists CHIPNAME] } {
   4    set  _CHIPNAME $CHIPNAME
   5 } else {
   6    set  _CHIPNAME lm3s
   7 }
   8
   9 # CPU TAP ID 0x1ba00477 for early Sandstorm parts
  10 # CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
  11 # CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
  12 # CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest)
  13 # ... we'll ignore the JTAG version field, rather than list every
  14 # chip revision that turns up.
  15 if { [info exists CPUTAPID ] } {
  16    set _CPUTAPID $CPUTAPID
  17 } else {
  18    set _CPUTAPID 0x0ba00477
  19 }
  20
  21 if { [info exists WORKAREASIZE ] } {
  22    set _WORKAREASIZE $WORKAREASIZE
  23 } else {
  24    # default to 8K working area
  25    set _WORKAREASIZE 0x2000
  26 }
  27
  28 jtag newtap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
  29         -expected-id $_CPUTAPID -ignore-version
  30
  31 set _TARGETNAME $_CHIPNAME.cpu
  32 target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
  33
  34 # 8K working area at base of ram, not backed up
  35 #
  36 # NOTE:  you may need or want to reconfigure the work area;
  37 # some parts have just 6K, and you may want to use other
  38 # addresses (at end of mem not beginning) or back it up.
  39 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
  40
  41 # JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
  42 # LM3S parts don't support RTCK
  43 #
  44 # NOTE:  this may be increased by a reset-init handler, after it
  45 # configures and enables the PLL.  Or you might need to decrease
  46 # this, if you're using a slower clock.
  47 adapter_khz 500
  48
  49 # mrw: "memory read word", returns value of $reg
  50 proc mrw {reg} {
  51         set value ""
  52         mem2array value 32 $reg 1
  53         return $value(0)
  54 }
  55
  56 $_TARGETNAME configure -event reset-start {
  57         adapter_khz 500
  58
  59         #
  60         # When nRST is asserted on most Stellaris devices, it clears some of
  61         # the debug state.  The ARMv7M and Cortex-M3 TRMs say that's wrong;
  62         # and OpenOCD depends on those TRMs.  So we won't use SRST on those
  63         # chips.  (Only power-on reset should affect debug state, beyond a
  64         # few specified bits; not the chip's nRST input, wired to SRST.)
  65         #
  66         # REVISIT current errata specs don't seem to cover this issue.
  67         # Do we have more details than this email?
  68         #   https://lists.berlios.de/pipermail
  69         #       /openocd-development/2008-August/003065.html
  70         #
  71
  72         set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)]
  73         if {$device_class == 0 || $device_class == 1 || $device_class == 3} {
  74                 # Sandstorm, Fury and DustDevil are able to use NVIC SYSRESETREQ
  75                 cortex_m3 reset_config systesetreq
  76         } else {
  77                 # Tempest and newer default to using NVIC VECTRESET
  78                 # this does mean a reset-init event handler is required to reset
  79                 # any peripherals
  80                 cortex_m3 reset_config vectreset
  81         }
  82 }
  83
  84 # flash configuration ... autodetects sizes, autoprobed
  85 flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME
  86