1 # TI/Luminary Stellaris LM3S chip family
3 if { [info exists CHIPNAME] } {
4 set _CHIPNAME $CHIPNAME
9 # CPU TAP ID 0x1ba00477 for early Sandstorm parts
10 # CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
11 # CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
12 # CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest)
13 # ... we'll ignore the JTAG version field, rather than list every
14 # chip revision that turns up.
15 if { [info exists CPUTAPID ] } {
16 set _CPUTAPID $CPUTAPID
18 set _CPUTAPID 0x0ba00477
21 jtag newtap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
22 -expected-id $_CPUTAPID -ignore-version
24 # The "lm3s" variant uses a software reset rather than SRST.
25 # This stops the debug registers from being cleared; it works
26 # around an erratum which should be fixed in later silicon.
27 set _TARGETNAME $_CHIPNAME.cpu
28 target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu \
31 # 8K working area at base of ram, not backed up
33 # NOTE: you may need or want to reconfigure the work area;
34 # some parts have just 6K, and you may want to use other
35 # addresses (at end of mem not beginning) or back it up.
36 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
38 # JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
39 # LM3S parts don't support RTCK
41 # NOTE: this may be increased by a reset-init handler, after it
42 # configures and enables the PLL. Or you might need to decrease
43 # this, if you're using a slower clock.
45 $_TARGETNAME configure -event reset-start {adapter_khz 500}
47 # flash configuration ... autodetects sizes, autoprobed
48 flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)