tcl/target/stellaris.cfg

   1 # TI/Luminary Stellaris LM3S chip family
   2
   3 # Some devices have errata in returning their device class.
   4 # DEVICECLASS is provided as a manual override
   5 # Manual setting of a device class of 0xff is not allowed
   6
   7 global _DEVICECLASS
   8
   9 if { [info exists DEVICECLASS] } {
  10    set _DEVICECLASS $DEVICECLASS
  11 } else {
  12    set _DEVICECLASS 0xff
  13 }
  14
  15 # Luminary chips support both JTAG and SWD transports.
  16 # Adapt based on what transport is active.
  17 source [find target/swj-dp.tcl]
  18
  19 # For now we ignore the SPI and UART options, which
  20 # are usable only for ISP style initial flash programming.
  21
  22 if { [info exists CHIPNAME] } {
  23    set _CHIPNAME $CHIPNAME
  24 } else {
  25    set _CHIPNAME lm3s
  26 }
  27
  28 # CPU TAP ID 0x1ba00477 for early Sandstorm parts
  29 # CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
  30 # CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
  31 # CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest)
  32 # ... we'll ignore the JTAG version field, rather than list every
  33 # chip revision that turns up.
  34 if { [info exists CPUTAPID] } {
  35    set _CPUTAPID $CPUTAPID
  36 } else {
  37    set _CPUTAPID 0x0ba00477
  38 }
  39
  40 # SWD DAP, and JTAG TAP, take same params for now;
  41 # ... even though SWD ignores all except TAPID, and
  42 # JTAG shouldn't need anything more then irlen. (and TAPID).
  43 swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
  44         -expected-id $_CPUTAPID -ignore-version
  45
  46 if { [info exists WORKAREASIZE] } {
  47    set _WORKAREASIZE $WORKAREASIZE
  48 } else {
  49    # default to 8K working area
  50    set _WORKAREASIZE 0x2000
  51 }
  52
  53 set _TARGETNAME $_CHIPNAME.cpu
  54 target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
  55
  56 # 8K working area at base of ram, not backed up
  57 #
  58 # NOTE: you may need or want to reconfigure the work area;
  59 # some parts have just 6K, and you may want to use other
  60 # addresses (at end of mem not beginning) or back it up.
  61 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
  62
  63 # JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
  64 # LM3S parts don't support RTCK
  65 #
  66 # NOTE: this may be increased by a reset-init handler, after it
  67 # configures and enables the PLL.  Or you might need to decrease
  68 # this, if you're using a slower clock.
  69 adapter_khz 500
  70
  71 source [find mem_helper.tcl]
  72
  73 proc reset_peripherals {family} {
  74
  75         source [find chip/ti/lm3s/lm3s.tcl]
  76
  77         echo "Resetting Core Peripherals"
  78
  79         # Disable the PLL and the system clock divider (nop if disabled)
  80         mmw $SYSCTL_RCC 0 $SYSCTL_RCC_USESYSDIV
  81         mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0
  82
  83         # RCC and RCC2 to their reset values
  84         mww $SYSCTL_RCC [expr (0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS))]
  85         mww $SYSCTL_RCC2 0x07806810
  86         mww $SYSCTL_RCC 0x078e3ad1
  87
  88         # Reset the deep sleep clock configuration register
  89         mww $SYSCTL_DSLPCLKCFG 0x07800000
  90
  91         # Reset the clock gating registers
  92         mww $SYSCTL_RCGC0 0x00000040
  93         mww $SYSCTL_RCGC1 0
  94         mww $SYSCTL_RCGC2 0
  95         mww $SYSCTL_SCGC0 0x00000040
  96         mww $SYSCTL_SCGC1 0
  97         mww $SYSCTL_SCGC2 0
  98         mww $SYSCTL_DCGC0 0x00000040
  99         mww $SYSCTL_DCGC1 0
 100         mww $SYSCTL_DCGC2 0
 101
 102         # Reset the remaining SysCtl registers
 103         mww $SYSCTL_PBORCTL 0
 104         mww $SYSCTL_IMC 0
 105         mww $SYSCTL_GPIOHBCTL 0
 106         mww $SYSCTL_MOSCCTL 0
 107         mww $SYSCTL_PIOSCCAL 0
 108         mww $SYSCTL_I2SMCLKCFG 0
 109
 110         # Reset the peripherals
 111         mww $SYSCTL_SRCR0 0xffffffff
 112         mww $SYSCTL_SRCR1 0xffffffff
 113         mww $SYSCTL_SRCR2 0xffffffff
 114         mww $SYSCTL_SRCR0 0
 115         mww $SYSCTL_SRCR1 0
 116         mww $SYSCTL_SRCR2 0
 117
 118         # Clear any pending SysCtl interrupts
 119         mww $SYSCTL_MISC 0xffffffff
 120
 121         # Wait for any pending flash operations to complete
 122         while {[expr [mrw $FLASH_FMC] & 0xffff] != 0} { sleep 1 }
 123         while {[expr [mrw $FLASH_FMC2] & 0xffff] != 0} { sleep 1 }
 124
 125         # Reset the flash controller registers
 126         mww $FLASH_FMA 0
 127         mww $FLASH_FCIM 0
 128         mww $FLASH_FCMISC 0xffffffff
 129         mww $FLASH_FWBVAL 0
 130 }
 131
 132 $_TARGETNAME configure -event reset-start {
 133         adapter_khz 500
 134
 135         #
 136         # When nRST is asserted on most Stellaris devices, it clears some of
 137         # the debug state.  The ARMv7M and Cortex-M3 TRMs say that's wrong;
 138         # and OpenOCD depends on those TRMs.  So we won't use SRST on those
 139         # chips.  (Only power-on reset should affect debug state, beyond a
 140         # few specified bits; not the chip's nRST input, wired to SRST.)
 141         #
 142         # REVISIT current errata specs don't seem to cover this issue.
 143         # Do we have more details than this email?
 144         #   https://lists.berlios.de/pipermail
 145         #       /openocd-development/2008-August/003065.html
 146         #
 147
 148         global _DEVICECLASS
 149
 150         if {$_DEVICECLASS != 0xff} {
 151            set device_class $_DEVICECLASS
 152         } else {
 153            set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)]
 154         }
 155
 156         if {$device_class == 0 || $device_class == 1 ||
 157                 $device_class == 3 || $device_class == 5} {
 158                 # Sandstorm, Fury, DustDevil and Blizzard are able to use NVIC SYSRESETREQ
 159                 cortex_m3 reset_config sysresetreq
 160         } else {
 161                 # Tempest and Firestorm default to using NVIC VECTRESET
 162                 # peripherals will need reseting manually, see proc reset_peripherals
 163                 cortex_m3 reset_config vectreset
 164
 165                 # reset peripherals, based on code in
 166                 # http://www.ti.com/lit/er/spmz573a/spmz573a.pdf
 167                 reset_peripherals $device_class
 168         }
 169 }
 170
 171 # flash configuration ... autodetects sizes, autoprobed
 172 flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME