tcl/target/stm32f0x.cfg

   1 # script for stm32f0x family
   2
   3 #
   4 # stm32 devices support SWD transports only.
   5 #
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10    set _CHIPNAME $CHIPNAME
  11 } else {
  12    set _CHIPNAME stm32f0x
  13 }
  14
  15 set _ENDIAN little
  16
  17 # Work-area is a space in RAM used for flash programming
  18 # By default use 4kB
  19 if { [info exists WORKAREASIZE] } {
  20    set _WORKAREASIZE $WORKAREASIZE
  21 } else {
  22    set _WORKAREASIZE 0x1000
  23 }
  24
  25 #jtag scan chain
  26 if { [info exists CPUTAPID] } {
  27    set _CPUTAPID $CPUTAPID
  28 } else {
  29   # See STM Document RM0091
  30   # Section 29.5.3
  31    set _CPUTAPID 0x0bb11477
  32 }
  33
  34 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  35
  36 set _TARGETNAME $_CHIPNAME.cpu
  37 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  38
  39 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  40
  41 # flash size will be probed
  42 set _FLASHNAME $_CHIPNAME.flash
  43 flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
  44
  45 # adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
  46 adapter_khz 1000
  47
  48 adapter_nsrst_delay 100
  49
  50 reset_config srst_nogate
  51
  52 if {![using_hla]} {
  53    # if srst is not fitted use SYSRESETREQ to
  54    # perform a soft reset
  55    cortex_m reset_config sysresetreq
  56 }
  57
  58 proc stm32f0x_default_reset_start {} {
  59         # Reset clock is HSI (8 MHz)
  60         adapter_khz 1000
  61 }
  62
  63 proc stm32f0x_default_examine_end {} {
  64         # Enable debug during low power modes (uses more power)
  65         mmw 0x40015804 0x00000006 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
  66
  67         # Stop watchdog counters during halt
  68         mmw 0x40015808 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
  69 }
  70
  71 proc stm32f0x_default_reset_init {} {
  72         # Configure PLL to boost clock to HSI x 6 (48 MHz)
  73         mww 0x40021004 0x00100000   ;# RCC_CFGR = PLLMUL[2]
  74         mmw 0x40021000 0x01000000 0 ;# RCC_CR[31:16] |= PLLON
  75         mww 0x40022000 0x00000011   ;# FLASH_ACR = PRFTBE | LATENCY[0]
  76         sleep 10                    ;# Wait for PLL to lock
  77         mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
  78
  79         # Boost JTAG frequency
  80         adapter_khz 8000
  81 }
  82
  83 # Default hooks
  84 $_TARGETNAME configure -event examine-end { stm32f0x_default_examine_end }
  85 $_TARGETNAME configure -event reset-start { stm32f0x_default_reset_start }
  86 $_TARGETNAME configure -event reset-init { stm32f0x_default_reset_init }