tcl/target/stm32f0x.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # script for stm32f0x family
   4
   5 #
   6 # stm32 devices support SWD transports only.
   7 #
   8 source [find target/swj-dp.tcl]
   9 source [find mem_helper.tcl]
  10
  11 if { [info exists CHIPNAME] } {
  12    set _CHIPNAME $CHIPNAME
  13 } else {
  14    set _CHIPNAME stm32f0x
  15 }
  16
  17 set _ENDIAN little
  18
  19 # Work-area is a space in RAM used for flash programming
  20 # By default use 4kB
  21 if { [info exists WORKAREASIZE] } {
  22    set _WORKAREASIZE $WORKAREASIZE
  23 } else {
  24    set _WORKAREASIZE 0x1000
  25 }
  26
  27 # Allow overriding the Flash bank size
  28 if { [info exists FLASH_SIZE] } {
  29         set _FLASH_SIZE $FLASH_SIZE
  30 } else {
  31         # autodetect size
  32         set _FLASH_SIZE 0
  33 }
  34
  35 #jtag scan chain
  36 if { [info exists CPUTAPID] } {
  37    set _CPUTAPID $CPUTAPID
  38 } else {
  39   # See STM Document RM0091
  40   # Section 29.5.3
  41    set _CPUTAPID 0x0bb11477
  42 }
  43
  44 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  45 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  46
  47 set _TARGETNAME $_CHIPNAME.cpu
  48 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  49
  50 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  51
  52 # flash size will be probed
  53 set _FLASHNAME $_CHIPNAME.flash
  54 flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
  55
  56 # adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
  57 adapter speed 1000
  58
  59 adapter srst delay 100
  60
  61 reset_config srst_nogate
  62
  63 if {![using_hla]} {
  64    # if srst is not fitted use SYSRESETREQ to
  65    # perform a soft reset
  66    cortex_m reset_config sysresetreq
  67 }
  68
  69 proc stm32f0x_default_reset_start {} {
  70         # Reset clock is HSI (8 MHz)
  71         adapter speed 1000
  72 }
  73
  74 proc stm32f0x_default_examine_end {} {
  75         # Enable debug during low power modes (uses more power)
  76         mmw 0x40015804 0x00000006 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
  77
  78         # Stop watchdog counters during halt
  79         mmw 0x40015808 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
  80 }
  81
  82 proc stm32f0x_default_reset_init {} {
  83         # Configure PLL to boost clock to HSI x 6 (48 MHz)
  84         mww 0x40021004 0x00100000   ;# RCC_CFGR = PLLMUL[2]
  85         mmw 0x40021000 0x01000000 0 ;# RCC_CR[31:16] |= PLLON
  86         mww 0x40022000 0x00000011   ;# FLASH_ACR = PRFTBE | LATENCY[0]
  87         sleep 10                    ;# Wait for PLL to lock
  88         mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
  89
  90         # Boost JTAG frequency
  91         adapter speed 8000
  92 }
  93
  94 # Default hooks
  95 $_TARGETNAME configure -event examine-end { stm32f0x_default_examine_end }
  96 $_TARGETNAME configure -event reset-start { stm32f0x_default_reset_start }
  97 $_TARGETNAME configure -event reset-init { stm32f0x_default_reset_init }