tcl/target/stm32f0x.cfg

   1 # script for stm32f0x family
   2
   3 #
   4 # stm32 devices support SWD transports only.
   5 #
   6 source [find target/swj-dp.tcl]
   7
   8 if { [info exists CHIPNAME] } {
   9    set _CHIPNAME $CHIPNAME
  10 } else {
  11    set _CHIPNAME stm32f0x
  12 }
  13
  14 if { [info exists ENDIAN] } {
  15    set _ENDIAN $ENDIAN
  16 } else {
  17    set _ENDIAN little
  18 }
  19
  20 # Work-area is a space in RAM used for flash programming
  21 # By default use 4kB
  22 if { [info exists WORKAREASIZE] } {
  23    set _WORKAREASIZE $WORKAREASIZE
  24 } else {
  25    set _WORKAREASIZE 0x1000
  26 }
  27
  28 #jtag scan chain
  29 if { [info exists CPUTAPID] } {
  30    set _CPUTAPID $CPUTAPID
  31 } else {
  32   # See STM Document RM0091
  33   # Section 29.5.3
  34    set _CPUTAPID 0x0bb11477
  35 }
  36
  37 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  38
  39 set _TARGETNAME $_CHIPNAME.cpu
  40 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  41
  42 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  43
  44 # flash size will be probed
  45 set _FLASHNAME $_CHIPNAME.flash
  46 flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
  47
  48 # adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
  49 adapter_khz 1000
  50
  51 adapter_nsrst_delay 100
  52
  53 if {![using_hla]} {
  54    # if srst is not fitted use SYSRESETREQ to
  55    # perform a soft reset
  56    cortex_m reset_config sysresetreq
  57 }