tcl/target/stm32f1x.cfg

   1 # script for stm32f1x family
   2
   3 #
   4 # stm32 devices support both JTAG and SWD transports.
   5 #
   6 source [find target/swj-dp.tcl]
   7
   8 if { [info exists CHIPNAME] } {
   9    set _CHIPNAME $CHIPNAME
  10 } else {
  11    set _CHIPNAME stm32f1x
  12 }
  13
  14 if { [info exists ENDIAN] } {
  15    set _ENDIAN $ENDIAN
  16 } else {
  17    set _ENDIAN little
  18 }
  19
  20 # Work-area is a space in RAM used for flash programming
  21 # By default use 4kB (as found on some STM32F100s)
  22 if { [info exists WORKAREASIZE] } {
  23    set _WORKAREASIZE $WORKAREASIZE
  24 } else {
  25    set _WORKAREASIZE 0x1000
  26 }
  27
  28 #jtag scan chain
  29 if { [info exists CPUTAPID] } {
  30    set _CPUTAPID $CPUTAPID
  31 } else {
  32    if { [using_jtag] } {
  33       # See STM Document RM0008 Section 26.6.3
  34       set _CPUTAPID 0x3ba00477
  35    } {
  36       # this is the SW-DP tap id not the jtag tap id
  37       set _CPUTAPID 0x1ba01477
  38    }
  39 }
  40
  41 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  42
  43 if { [info exists BSTAPID] } {
  44    # FIXME this never gets used to override defaults...
  45    set _BSTAPID $BSTAPID
  46 } else {
  47   # See STM Document RM0008
  48   # Section 29.6.2
  49   # Low density devices, Rev A
  50   set _BSTAPID1 0x06412041
  51   # Medium density devices, Rev A
  52   set _BSTAPID2 0x06410041
  53   # Medium density devices, Rev B and Rev Z
  54   set _BSTAPID3 0x16410041
  55   set _BSTAPID4 0x06420041
  56   # High density devices, Rev A
  57   set _BSTAPID5 0x06414041
  58   # Connectivity line devices, Rev A and Rev Z
  59   set _BSTAPID6 0x06418041
  60   # XL line devices, Rev A
  61   set _BSTAPID7 0x06430041
  62   # VL line devices, Rev A and Z In medium-density and high-density value line devices
  63   set _BSTAPID8 0x06420041
  64   # VL line devices, Rev A
  65   set _BSTAPID9 0x06428041
  66 }
  67
  68 if {[using_jtag]} {
  69  swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
  70         -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
  71         -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \
  72         -expected-id $_BSTAPID6 -expected-id $_BSTAPID7 \
  73         -expected-id $_BSTAPID8 -expected-id $_BSTAPID9
  74 }
  75
  76 set _TARGETNAME $_CHIPNAME.cpu
  77 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  78
  79 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  80
  81 # flash size will be probed
  82 set _FLASHNAME $_CHIPNAME.flash
  83 flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
  84
  85 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
  86 adapter_khz 1000
  87
  88 adapter_nsrst_delay 100
  89 if {[using_jtag]} {
  90  jtag_ntrst_delay 100
  91 }
  92
  93 if {![using_hla]} {
  94     # if srst is not fitted use SYSRESETREQ to
  95     # perform a soft reset
  96     cortex_m reset_config sysresetreq
  97 }