tcl/target/stm32f1x.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # script for stm32f1x family
   4
   5 #
   6 # stm32 devices support both JTAG and SWD transports.
   7 #
   8 source [find target/swj-dp.tcl]
   9 source [find mem_helper.tcl]
  10
  11 if { [info exists CHIPNAME] } {
  12    set _CHIPNAME $CHIPNAME
  13 } else {
  14    set _CHIPNAME stm32f1x
  15 }
  16
  17 set _ENDIAN little
  18
  19 # Work-area is a space in RAM used for flash programming
  20 # By default use 4kB (as found on some STM32F100s)
  21 if { [info exists WORKAREASIZE] } {
  22    set _WORKAREASIZE $WORKAREASIZE
  23 } else {
  24    set _WORKAREASIZE 0x1000
  25 }
  26
  27 # Allow overriding the Flash bank size
  28 if { [info exists FLASH_SIZE] } {
  29     set _FLASH_SIZE $FLASH_SIZE
  30 } else {
  31     # autodetect size
  32     set _FLASH_SIZE 0
  33 }
  34
  35 #jtag scan chain
  36 if { [info exists CPUTAPID] } {
  37    set _CPUTAPID $CPUTAPID
  38 } else {
  39    if { [using_jtag] } {
  40       # See STM Document RM0008 Section 26.6.3
  41       set _CPUTAPID 0x3ba00477
  42    } {
  43       # this is the SW-DP tap id not the jtag tap id
  44       set _CPUTAPID 0x1ba01477
  45    }
  46 }
  47
  48 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  49 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  50
  51 if {[using_jtag]} {
  52    jtag newtap $_CHIPNAME bs -irlen 5
  53 }
  54
  55 set _TARGETNAME $_CHIPNAME.cpu
  56 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  57
  58 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  59
  60 # flash size will be probed
  61 set _FLASHNAME $_CHIPNAME.flash
  62 flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
  63
  64 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
  65 adapter speed 1000
  66
  67 adapter srst delay 100
  68 if {[using_jtag]} {
  69  jtag_ntrst_delay 100
  70 }
  71
  72 reset_config srst_nogate
  73
  74 if {![using_hla]} {
  75     # if srst is not fitted use SYSRESETREQ to
  76     # perform a soft reset
  77     cortex_m reset_config sysresetreq
  78 }
  79
  80 $_TARGETNAME configure -event examine-end {
  81         # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
  82         #              DBG_STANDBY | DBG_STOP | DBG_SLEEP
  83         mmw 0xE0042004 0x00000307 0
  84 }
  85
  86 tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
  87
  88 lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
  89 proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
  90         targets $_targetname
  91
  92         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
  93         # change this value accordingly to configure trace pins
  94         # assignment
  95         mmw 0xE0042004 0x00000020 0
  96 }
  97
  98 $_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"