tcl/target/stm32f3x.cfg

   1 # script for stm32f3x family
   2
   3 #
   4 # stm32 devices support both JTAG and SWD transports.
   5 #
   6 source [find target/swj-dp.tcl]
   7
   8 if { [info exists CHIPNAME] } {
   9    set _CHIPNAME $CHIPNAME
  10 } else {
  11    set _CHIPNAME stm32f3x
  12 }
  13
  14 set _ENDIAN little
  15
  16 # Work-area is a space in RAM used for flash programming
  17 # By default use 16kB
  18 if { [info exists WORKAREASIZE] } {
  19    set _WORKAREASIZE $WORKAREASIZE
  20 } else {
  21    set _WORKAREASIZE 0x4000
  22 }
  23
  24 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
  25 #
  26 # Since we may be running of an RC oscilator, we crank down the speed a
  27 # bit more to be on the safe side. Perhaps superstition, but if are
  28 # running off a crystal, we can run closer to the limit. Note
  29 # that there can be a pretty wide band where things are more or less stable.
  30 adapter_khz 1000
  31
  32 adapter_nsrst_delay 100
  33 if {[using_jtag]} {
  34  jtag_ntrst_delay 100
  35 }
  36
  37 #jtag scan chain
  38 if { [info exists CPUTAPID] } {
  39    set _CPUTAPID $CPUTAPID
  40 } else {
  41    if { [using_jtag] } {
  42       # See STM Document RM0316
  43       # Section 29.6.3 - corresponds to Cortex-M4 r0p1
  44       set _CPUTAPID 0x4ba00477
  45    } {
  46       set _CPUTAPID 0x2ba01477
  47    }
  48 }
  49
  50 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  51
  52 if { [info exists BSTAPID] } {
  53    set _BSTAPID $BSTAPID
  54 } else {
  55   # STM Document RM0316 rev 5 for STM32F302/303 B/C size
  56   set _BSTAPID1 0x06422041
  57   # STM Document RM0313 rev 3 for STM32F37x
  58   set _BSTAPID2 0x06432041
  59   # STM Document RM0313 rev 3 for STM32F37x Chip Revision 1.0
  60   set _BSTAPID3 0x06422041
  61   #  STM Document RM364 rev 1 for STM32F334
  62   set _BSTAPID4 0x06438041
  63   #  STM Document RM316 rev 5 for STM32F303 6/8 size
  64   #  STM Document RM365 rev 3 for STM32F302 6/8 size
  65   #  STM Document RM366 rev 2 for STM32F301 6/8 size
  66   set _BSTAPID5 0x06439041
  67   #  STM Document RM016 rev 5 for STM32F303 D/E size
  68   set _BSTAPID6 0x06446041
  69 }
  70
  71 if {[using_jtag]} {
  72  swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
  73  -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 -expected-id $_BSTAPID4 \
  74  -expected-id $_BSTAPID5 -expected-id $_BSTAPID6
  75 }
  76
  77 set _TARGETNAME $_CHIPNAME.cpu
  78 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  79
  80 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  81
  82 set _FLASHNAME $_CHIPNAME.flash
  83 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
  84
  85 reset_config srst_nogate
  86
  87 if {![using_hla]} {
  88    # if srst is not fitted use SYSRESETREQ to
  89    # perform a soft reset
  90    cortex_m reset_config sysresetreq
  91 }