tcl/target/stm32f3x.cfg

   1 # script for stm32f3x family
   2
   3 if { [info exists CHIPNAME] } {
   4    set _CHIPNAME $CHIPNAME
   5 } else {
   6    set _CHIPNAME stm32f3x
   7 }
   8
   9 if { [info exists ENDIAN] } {
  10    set _ENDIAN $ENDIAN
  11 } else {
  12    set _ENDIAN little
  13 }
  14
  15 # Work-area is a space in RAM used for flash programming
  16 # By default use 16kB
  17 if { [info exists WORKAREASIZE] } {
  18    set _WORKAREASIZE $WORKAREASIZE
  19 } else {
  20    set _WORKAREASIZE 0x4000
  21 }
  22
  23 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
  24 #
  25 # Since we may be running of an RC oscilator, we crank down the speed a
  26 # bit more to be on the safe side. Perhaps superstition, but if are
  27 # running off a crystal, we can run closer to the limit. Note
  28 # that there can be a pretty wide band where things are more or less stable.
  29 adapter_khz 1000
  30
  31 adapter_nsrst_delay 100
  32 jtag_ntrst_delay 100
  33
  34 #jtag scan chain
  35 if { [info exists CPUTAPID] } {
  36    set _CPUTAPID $CPUTAPID
  37 } else {
  38   # See STM Document RM0316
  39   # Section 29.6.3 - corresponds to Cortex-M4 r0p1
  40    set _CPUTAPID 0x4ba00477
  41 }
  42 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  43
  44 if { [info exists BSTAPID] } {
  45    set _BSTAPID $BSTAPID
  46 } else {
  47   # STM Document RM0316 rev 2 Section 30.6.2 says 0x06432041
  48   # but STM32F303VCT6 rev Y has 0x06422041
  49   set _BSTAPID1 0x06422041
  50   set _BSTAPID2 0x06432041
  51 }
  52 jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
  53
  54 set _TARGETNAME $_CHIPNAME.cpu
  55 target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
  56
  57 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  58
  59 set _FLASHNAME $_CHIPNAME.flash
  60 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
  61
  62 # if srst is not fitted use SYSRESETREQ to
  63 # perform a soft reset
  64 cortex_m3 reset_config sysresetreq