tcl/target/stm32f3x.cfg

   1 # script for stm32f3x family
   2
   3 #
   4 # stm32 devices support both JTAG and SWD transports.
   5 #
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10    set _CHIPNAME $CHIPNAME
  11 } else {
  12    set _CHIPNAME stm32f3x
  13 }
  14
  15 set _ENDIAN little
  16
  17 # Work-area is a space in RAM used for flash programming
  18 # By default use 16kB
  19 if { [info exists WORKAREASIZE] } {
  20    set _WORKAREASIZE $WORKAREASIZE
  21 } else {
  22    set _WORKAREASIZE 0x4000
  23 }
  24
  25 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
  26 #
  27 # Since we may be running of an RC oscilator, we crank down the speed a
  28 # bit more to be on the safe side. Perhaps superstition, but if are
  29 # running off a crystal, we can run closer to the limit. Note
  30 # that there can be a pretty wide band where things are more or less stable.
  31 adapter_khz 1000
  32
  33 adapter_nsrst_delay 100
  34 if {[using_jtag]} {
  35  jtag_ntrst_delay 100
  36 }
  37
  38 #jtag scan chain
  39 if { [info exists CPUTAPID] } {
  40    set _CPUTAPID $CPUTAPID
  41 } else {
  42    if { [using_jtag] } {
  43       # See STM Document RM0316
  44       # Section 29.6.3 - corresponds to Cortex-M4 r0p1
  45       set _CPUTAPID 0x4ba00477
  46    } {
  47       set _CPUTAPID 0x2ba01477
  48    }
  49 }
  50
  51 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  52
  53 if { [info exists BSTAPID] } {
  54    set _BSTAPID $BSTAPID
  55 } else {
  56   # STM Document RM0316 rev 5 for STM32F302/303 B/C size
  57   set _BSTAPID1 0x06422041
  58   # STM Document RM0313 rev 3 for STM32F37x
  59   set _BSTAPID2 0x06432041
  60   #  STM Document RM364 rev 1 for STM32F334
  61   set _BSTAPID3 0x06438041
  62   #  STM Document RM316 rev 5 for STM32F303 6/8 size
  63   #  STM Document RM365 rev 3 for STM32F302 6/8 size
  64   #  STM Document RM366 rev 2 for STM32F301 6/8 size
  65   set _BSTAPID4 0x06439041
  66   #  STM Document RM016 rev 5 for STM32F303 D/E size
  67   set _BSTAPID5 0x06446041
  68 }
  69
  70 if {[using_jtag]} {
  71  swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
  72  -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
  73  -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
  74 }
  75
  76 set _TARGETNAME $_CHIPNAME.cpu
  77 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  78
  79 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  80
  81 set _FLASHNAME $_CHIPNAME.flash
  82 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
  83
  84 reset_config srst_nogate
  85
  86 if {![using_hla]} {
  87    # if srst is not fitted use SYSRESETREQ to
  88    # perform a soft reset
  89    cortex_m reset_config sysresetreq
  90 }
  91
  92 proc stm32f3x_default_reset_start {} {
  93         # Reset clock is HSI (8 MHz)
  94         adapter_khz 1000
  95 }
  96
  97 proc stm32f3x_default_examine_end {} {
  98         # Enable debug during low power modes (uses more power)
  99         mmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
 100
 101         # Stop watchdog counters during halt
 102         mww 0xe0042008 0x00001800 ;# DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
 103 }
 104
 105 proc stm32f3x_default_reset_init {} {
 106         # Configure PLL to boost clock to HSI x 8 (64 MHz)
 107         mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
 108         mwh 0x40021002 0x0100     ;# RCC_CR[31:16] = PLLON
 109         mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1]
 110         sleep 10                  ;# Wait for PLL to lock
 111         mww 0x40021004 0x00380402 ;# RCC_CFGR |= SW[1]
 112
 113         # Boost JTAG frequency
 114         adapter_khz 8000
 115 }
 116
 117 # Default hooks
 118 $_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end }
 119 $_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start }
 120 $_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init }