tcl/target/stm32f3x.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # script for stm32f3x family
   4
   5 #
   6 # stm32 devices support both JTAG and SWD transports.
   7 #
   8 source [find target/swj-dp.tcl]
   9 source [find mem_helper.tcl]
  10
  11 if { [info exists CHIPNAME] } {
  12    set _CHIPNAME $CHIPNAME
  13 } else {
  14    set _CHIPNAME stm32f3x
  15 }
  16
  17 set _ENDIAN little
  18
  19 # Work-area is a space in RAM used for flash programming
  20 # By default use 16kB
  21 if { [info exists WORKAREASIZE] } {
  22    set _WORKAREASIZE $WORKAREASIZE
  23 } else {
  24    set _WORKAREASIZE 0x4000
  25 }
  26
  27 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
  28 #
  29 # Since we may be running of an RC oscilator, we crank down the speed a
  30 # bit more to be on the safe side. Perhaps superstition, but if are
  31 # running off a crystal, we can run closer to the limit. Note
  32 # that there can be a pretty wide band where things are more or less stable.
  33 adapter speed 1000
  34
  35 adapter srst delay 100
  36 if {[using_jtag]} {
  37  jtag_ntrst_delay 100
  38 }
  39
  40 #jtag scan chain
  41 if { [info exists CPUTAPID] } {
  42    set _CPUTAPID $CPUTAPID
  43 } else {
  44    if { [using_jtag] } {
  45       # See STM Document RM0316
  46       # Section 29.6.3 - corresponds to Cortex-M4 r0p1
  47       set _CPUTAPID 0x4ba00477
  48    } {
  49       set _CPUTAPID 0x2ba01477
  50    }
  51 }
  52
  53 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  54 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  55
  56 if {[using_jtag]} {
  57    jtag newtap $_CHIPNAME bs -irlen 5
  58 }
  59
  60 set _TARGETNAME $_CHIPNAME.cpu
  61 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  62
  63 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  64
  65 set _FLASHNAME $_CHIPNAME.flash
  66 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
  67
  68 reset_config srst_nogate
  69
  70 if {![using_hla]} {
  71    # if srst is not fitted use SYSRESETREQ to
  72    # perform a soft reset
  73    cortex_m reset_config sysresetreq
  74 }
  75
  76 proc stm32f3x_default_reset_start {} {
  77         # Reset clock is HSI (8 MHz)
  78         adapter speed 1000
  79 }
  80
  81 proc stm32f3x_default_examine_end {} {
  82         # Enable debug during low power modes (uses more power)
  83         mmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  84
  85         # Stop watchdog counters during halt
  86         mmw 0xe0042008 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
  87 }
  88
  89 proc stm32f3x_default_reset_init {} {
  90         # Configure PLL to boost clock to HSI x 8 (64 MHz)
  91         mww 0x40021004 0x00380400   ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
  92         mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON
  93         mww 0x40022000 0x00000012   ;# FLASH_ACR = PRFTBE | LATENCY[1]
  94         sleep 10                    ;# Wait for PLL to lock
  95         mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
  96
  97         # Boost JTAG frequency
  98         adapter speed 8000
  99 }
 100
 101 # Default hooks
 102 $_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end }
 103 $_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start }
 104 $_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init }
 105
 106 $_TARGETNAME configure -event trace-config {
 107         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
 108         # change this value accordingly to configure trace pins
 109         # assignment
 110         mmw 0xe0042004 0x00000020 0
 111 }