tcl/target/stm32f3x.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # script for stm32f3x family
   4
   5 #
   6 # stm32 devices support both JTAG and SWD transports.
   7 #
   8 source [find target/swj-dp.tcl]
   9 source [find mem_helper.tcl]
  10
  11 if { [info exists CHIPNAME] } {
  12    set _CHIPNAME $CHIPNAME
  13 } else {
  14    set _CHIPNAME stm32f3x
  15 }
  16
  17 set _ENDIAN little
  18
  19 # Work-area is a space in RAM used for flash programming
  20 # By default use 16kB
  21 if { [info exists WORKAREASIZE] } {
  22    set _WORKAREASIZE $WORKAREASIZE
  23 } else {
  24    set _WORKAREASIZE 0x4000
  25 }
  26
  27 # Allow overriding the Flash bank size
  28 if { [info exists FLASH_SIZE] } {
  29    set _FLASH_SIZE $FLASH_SIZE
  30 } else {
  31    # autodetect size
  32    set _FLASH_SIZE 0
  33 }
  34
  35 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
  36 #
  37 # Since we may be running of an RC oscilator, we crank down the speed a
  38 # bit more to be on the safe side. Perhaps superstition, but if are
  39 # running off a crystal, we can run closer to the limit. Note
  40 # that there can be a pretty wide band where things are more or less stable.
  41 adapter speed 1000
  42
  43 adapter srst delay 100
  44 if {[using_jtag]} {
  45  jtag_ntrst_delay 100
  46 }
  47
  48 #jtag scan chain
  49 if { [info exists CPUTAPID] } {
  50    set _CPUTAPID $CPUTAPID
  51 } else {
  52    if { [using_jtag] } {
  53       # See STM Document RM0316
  54       # Section 29.6.3 - corresponds to Cortex-M4 r0p1
  55       set _CPUTAPID 0x4ba00477
  56    } {
  57       set _CPUTAPID 0x2ba01477
  58    }
  59 }
  60
  61 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  62 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  63
  64 if {[using_jtag]} {
  65    jtag newtap $_CHIPNAME bs -irlen 5
  66 }
  67
  68 set _TARGETNAME $_CHIPNAME.cpu
  69 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  70
  71 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  72
  73 set _FLASHNAME $_CHIPNAME.flash
  74 flash bank $_FLASHNAME stm32f1x 0 $_FLASH_SIZE 0 0 $_TARGETNAME
  75
  76 reset_config srst_nogate
  77
  78 if {![using_hla]} {
  79    # if srst is not fitted use SYSRESETREQ to
  80    # perform a soft reset
  81    cortex_m reset_config sysresetreq
  82 }
  83
  84 proc stm32f3x_default_reset_start {} {
  85         # Reset clock is HSI (8 MHz)
  86         adapter speed 1000
  87 }
  88
  89 proc stm32f3x_default_examine_end {} {
  90         # Enable debug during low power modes (uses more power)
  91         mmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  92
  93         # Stop watchdog counters during halt
  94         mmw 0xe0042008 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
  95 }
  96
  97 proc stm32f3x_default_reset_init {} {
  98         # Configure PLL to boost clock to HSI x 8 (64 MHz)
  99         mww 0x40021004 0x00380400   ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
 100         mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON
 101         mww 0x40022000 0x00000012   ;# FLASH_ACR = PRFTBE | LATENCY[1]
 102         sleep 10                    ;# Wait for PLL to lock
 103         mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
 104
 105         # Boost JTAG frequency
 106         adapter speed 8000
 107 }
 108
 109 # Default hooks
 110 $_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end }
 111 $_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start }
 112 $_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init }
 113
 114 tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
 115
 116 lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
 117 proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
 118         targets $_targetname
 119
 120         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
 121         # change this value accordingly to configure trace pins
 122         # assignment
 123         mmw 0xe0042004 0x00000020 0
 124 }
 125
 126 $_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"