tcl/target/stm32f4x.cfg

   1 # script for stm32f4x family
   2
   3 #
   4 # stm32 devices support both JTAG and SWD transports.
   5 #
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10    set _CHIPNAME $CHIPNAME
  11 } else {
  12    set _CHIPNAME stm32f4x
  13 }
  14
  15 set _ENDIAN little
  16
  17 # Work-area is a space in RAM used for flash programming
  18 # By default use 32kB (Available RAM in smallest device STM32F410)
  19 if { [info exists WORKAREASIZE] } {
  20    set _WORKAREASIZE $WORKAREASIZE
  21 } else {
  22    set _WORKAREASIZE 0x8000
  23 }
  24
  25 #jtag scan chain
  26 if { [info exists CPUTAPID] } {
  27    set _CPUTAPID $CPUTAPID
  28 } else {
  29    if { [using_jtag] } {
  30       # See STM Document RM0090
  31       # Section 38.6.3 - corresponds to Cortex-M4 r0p1
  32       set _CPUTAPID 0x4ba00477
  33    } {
  34       set _CPUTAPID 0x2ba01477
  35    }
  36 }
  37
  38 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  39 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  40
  41 if {[using_jtag]} {
  42    jtag newtap $_CHIPNAME bs -irlen 5
  43 }
  44
  45 set _TARGETNAME $_CHIPNAME.cpu
  46 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  47
  48 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  49
  50 set _FLASHNAME $_CHIPNAME.flash
  51 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
  52
  53 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
  54 #
  55 # Since we may be running of an RC oscilator, we crank down the speed a
  56 # bit more to be on the safe side. Perhaps superstition, but if are
  57 # running off a crystal, we can run closer to the limit. Note
  58 # that there can be a pretty wide band where things are more or less stable.
  59 adapter_khz 2000
  60
  61 adapter_nsrst_delay 100
  62 if {[using_jtag]} {
  63  jtag_ntrst_delay 100
  64 }
  65
  66 reset_config srst_nogate
  67
  68 if {![using_hla]} {
  69    # if srst is not fitted use SYSRESETREQ to
  70    # perform a soft reset
  71    cortex_m reset_config sysresetreq
  72 }
  73
  74 $_TARGETNAME configure -event examine-end {
  75         # Enable debug during low power modes (uses more power)
  76         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  77         mmw 0xE0042004 0x00000007 0
  78
  79         # Stop watchdog counters during halt
  80         # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
  81         mmw 0xE0042008 0x00001800 0
  82 }
  83
  84 $_TARGETNAME configure -event trace-config {
  85         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
  86         # change this value accordingly to configure trace pins
  87         # assignment
  88         mmw 0xE0042004 0x00000020 0
  89 }
  90
  91 $_TARGETNAME configure -event reset-init {
  92         # Configure PLL to boost clock to HSI x 4 (64 MHz)
  93         mww 0x40023804 0x08012008   ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)
  94         mww 0x40023C00 0x00000102   ;# FLASH_ACR = PRFTBE | 2(Latency)
  95         mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
  96         sleep 10                    ;# Wait for PLL to lock
  97         mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
  98         mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
  99
 100         # Boost JTAG frequency
 101         adapter_khz 8000
 102 }
 103
 104 $_TARGETNAME configure -event reset-start {
 105         # Reduce speed since CPU speed will slow down to 16MHz with the reset
 106         adapter_khz 2000
 107 }