tcl/target/stm32f7x.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # script for stm32f7x family
   4
   5 #
   6 # stm32f7 devices support both JTAG and SWD transports.
   7 #
   8 source [find target/swj-dp.tcl]
   9 source [find mem_helper.tcl]
  10
  11 if { [info exists CHIPNAME] } {
  12    set _CHIPNAME $CHIPNAME
  13 } else {
  14    set _CHIPNAME stm32f7x
  15 }
  16
  17 set _ENDIAN little
  18
  19 # Work-area is a space in RAM used for flash programming
  20 # By default use 128kB
  21 if { [info exists WORKAREASIZE] } {
  22    set _WORKAREASIZE $WORKAREASIZE
  23 } else {
  24    set _WORKAREASIZE 0x20000
  25 }
  26
  27 #jtag scan chain
  28 if { [info exists CPUTAPID] } {
  29    set _CPUTAPID $CPUTAPID
  30 } else {
  31    if { [using_jtag] } {
  32       # See STM Document RM0385
  33       # Section 40.6.3 - corresponds to Cortex-M7 with FPU r0p0
  34       set _CPUTAPID 0x5ba00477
  35    } {
  36       set _CPUTAPID 0x5ba02477
  37    }
  38 }
  39
  40 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  41 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  42
  43 if {[using_jtag]} {
  44    jtag newtap $_CHIPNAME bs -irlen 5
  45 }
  46
  47 set _TARGETNAME $_CHIPNAME.cpu
  48 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  49
  50 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  51
  52 set _FLASHNAME $_CHIPNAME.flash
  53 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
  54 flash bank $_CHIPNAME.otp stm32f2x 0x1ff0f000 0 0 0 $_TARGETNAME
  55
  56 # On the STM32F7, the Flash is mapped at address 0x08000000 via the AXI and
  57 # also address 0x00200000 via the ITCM. The former mapping is read-write in
  58 # hardware, while the latter is read-only. By presenting an alias, we
  59 # accomplish two things:
  60 # (1) We allow writing at 0x00200000 (because the alias acts identically to the
  61 #     original bank), which allows code intended to run from that address to
  62 #     also be linked for loading at that address, simplifying linking.
  63 # (2) We allow the proper memory map to be delivered to GDB, which will cause
  64 #     it to use hardware breakpoints at the 0x00200000 mapping (correctly
  65 #     identifying it as Flash), which it would otherwise not do. Configuring
  66 #     the Flash via ITCM alias as virtual
  67 flash bank $_CHIPNAME.itcm-flash.alias virtual 0x00200000 0 0 0 $_TARGETNAME $_FLASHNAME
  68
  69 if { [info exists QUADSPI] && $QUADSPI } {
  70    set a [llength [flash list]]
  71    set _QSPINAME $_CHIPNAME.qspi
  72    flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
  73 }
  74
  75 # adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
  76 adapter speed 2000
  77
  78 adapter srst delay 100
  79 if {[using_jtag]} {
  80  jtag_ntrst_delay 100
  81 }
  82
  83 # Use hardware reset.
  84 #
  85 # This target is compatible with connect_assert_srst, which may be set in a
  86 # board file.
  87 reset_config srst_nogate
  88
  89 if {![using_hla]} {
  90    # if srst is not fitted use SYSRESETREQ to
  91    # perform a soft reset
  92    cortex_m reset_config sysresetreq
  93
  94    # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
  95    # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
  96    # makes the data access cacheable. This allows reading and writing data in the
  97    # CPU cache from the debugger, which is far more useful than going straight to
  98    # RAM when operating on typical variables, and is generally no worse when
  99    # operating on special memory locations.
 100    $_CHIPNAME.dap apcsw 0x08000000 0x08000000
 101 }
 102
 103 $_TARGETNAME configure -event examine-end {
 104         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
 105         mmw 0xE0042004 0x00000007 0
 106
 107         # Stop watchdog counters during halt
 108         # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
 109         mmw 0xE0042008 0x00001800 0
 110 }
 111
 112 $_TARGETNAME configure -event trace-config {
 113         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
 114         # change this value accordingly to configure trace pins
 115         # assignment
 116         mmw 0xE0042004 0x00000020 0
 117 }
 118
 119 $_TARGETNAME configure -event reset-init {
 120         # If the HSE was previously enabled and the external clock source
 121         # disappeared, RCC_CR.HSERDY can get stuck at 1 and the PLL cannot be
 122         # properly switched back to HSI. This situation persists even over a system
 123         # reset, including a pin reset via SRST. However, activating the clock
 124         # security system will detect the problem and clear HSERDY to 0, which in
 125         # turn allows the PLL to switch back to HSI properly. Since we just came
 126         # out of reset, HSEON should be 0. If HSERDY is 1, then this situation must
 127         # have happened; in that case, activate the clock security system to clear
 128         # HSERDY.
 129         if {[mrw 0x40023800] & 0x00020000} {
 130                 mmw 0x40023800 0x00090000 0 ;# RCC_CR = CSSON | HSEON
 131                 sleep 10                    ;# Wait for CSS to fire, if it wants to
 132                 mmw 0x40023800 0 0x00090000 ;# RCC_CR &= ~CSSON & ~HSEON
 133                 mww 0x4002380C 0x00800000   ;# RCC_CIR = CSSC
 134                 sleep 1                     ;# Wait for CSSF to clear
 135         }
 136
 137         # If the clock security system fired, it will pend an NMI. A pending NMI
 138         # will cause a bad time for any subsequent executing code, such as a
 139         # programming algorithm.
 140         if {[mrw 0xE000ED04] & 0x80000000} {
 141                 # ICSR.NMIPENDSET reads as 1. Need to clear it. A pending NMI can’t be
 142                 # cleared by any normal means (such as ICSR or NVIC). It can only be
 143                 # cleared by entering the NMI handler or by resetting the processor.
 144                 echo "[target current]: Clock security system generated NMI. Clearing."
 145
 146                 # Keep the old DEMCR value.
 147                 set old [mrw 0xE000EDFC]
 148
 149                 # Enable vector catch on reset.
 150                 mww 0xE000EDFC 0x01000001
 151
 152                 # Issue local reset via AIRCR.
 153                 mww 0xE000ED0C 0x05FA0001
 154
 155                 # Restore old DEMCR value.
 156                 mww 0xE000EDFC $old
 157         }
 158
 159         # Configure PLL to boost clock to HSI x 10 (160 MHz)
 160         mww 0x40023804 0x08002808   ;# RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P)
 161         mww 0x40023C00 0x00000107   ;# FLASH_ACR = PRFTBE | 7(Latency)
 162         mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
 163         sleep 10                    ;# Wait for PLL to lock
 164         mww 0x40023808 0x00009400   ;# RCC_CFGR_PPRE1 = 5(div 4), PPRE2 = 4(div 2)
 165         mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
 166
 167         # Boost SWD frequency
 168         # Do not boost JTAG frequency and slow down JTAG memory access or flash write algo
 169         # suffers from DAP WAITs
 170         if {[using_jtag]} {
 171                 [[target current] cget -dap] memaccess 16
 172         } {
 173                 adapter speed 8000
 174         }
 175 }
 176
 177 $_TARGETNAME configure -event reset-start {
 178         # Reduce speed since CPU speed will slow down to 16MHz with the reset
 179         adapter speed 2000
 180 }