tcl/target/stm32g0x.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # script for stm32g0x family
   4
   5 #
   6 # stm32g0 devices support SWD transports only.
   7 #
   8 source [find target/swj-dp.tcl]
   9 source [find mem_helper.tcl]
  10
  11 if { [info exists CHIPNAME] } {
  12         set _CHIPNAME $CHIPNAME
  13 } else {
  14         set _CHIPNAME stm32g0x
  15 }
  16
  17 set _ENDIAN little
  18
  19 # Work-area is a space in RAM used for flash programming
  20 # Smallest proposed target has 8kB ram, use 4kB by default to avoid surprises
  21 if { [info exists WORKAREASIZE] } {
  22         set _WORKAREASIZE $WORKAREASIZE
  23 } else {
  24         set _WORKAREASIZE 0x1000
  25 }
  26
  27 #jtag scan chain
  28 if { [info exists CPUTAPID] } {
  29         set _CPUTAPID $CPUTAPID
  30 } else {
  31         # Section 37.5.5 - corresponds to Cortex-M0+
  32         set _CPUTAPID 0x0bc11477
  33 }
  34
  35 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  36 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  37
  38 set _TARGETNAME $_CHIPNAME.cpu
  39 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  40
  41 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  42
  43 flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
  44 flash bank $_CHIPNAME.otp   stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
  45
  46 # reasonable default
  47 adapter speed 2000
  48
  49 adapter srst delay 100
  50 if {[using_jtag]} {
  51         jtag_ntrst_delay 100
  52 }
  53
  54 reset_config srst_nogate
  55
  56 if {![using_hla]} {
  57         # if srst is not fitted use SYSRESETREQ to
  58         # perform a soft reset
  59         cortex_m reset_config sysresetreq
  60 }
  61
  62 proc stm32g0x_default_reset_start {} {
  63         # Reset clock is HSI16 (16 MHz)
  64         adapter speed 2000
  65 }
  66
  67 proc stm32g0x_default_examine_end {} {
  68         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP
  69         mmw 0x40015804 0x00000006 0
  70
  71         # Stop watchdog counters during halt
  72         # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
  73         mmw 0x40015808 0x00001800 0
  74 }
  75
  76 proc stm32g0x_default_reset_init {} {
  77         # Increase clock to 64 Mhz
  78         mmw 0x40022000 0x00000002 0x00000005    ;# FLASH_ACR: Latency = 2
  79         mww 0x4002100C 0x30000802                               ;# RCC_PLLCFGR = PLLR=/2, PLLN=8, PLLM=/1, PLLSRC=0x2
  80         mmw 0x40021000 0x01000000 0x00000000    ;# RCC_CR |= PLLON
  81         mmw 0x40021008 0x00000002 0x00000005    ;# RCC_CFGR: SW=PLLRCLK
  82
  83         # Boost JTAG frequency
  84         adapter speed 4000
  85 }
  86
  87 # Default hooks
  88 $_TARGETNAME configure -event examine-end { stm32g0x_default_examine_end }
  89 $_TARGETNAME configure -event reset-start { stm32g0x_default_reset_start }
  90 $_TARGETNAME configure -event reset-init { stm32g0x_default_reset_init }