tcl/target/stm32h7x.cfg

   1 # script for stm32h7x family
   2
   3 #
   4 # stm32h7 devices support both JTAG and SWD transports.
   5 #
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10    set _CHIPNAME $CHIPNAME
  11 } else {
  12    set _CHIPNAME stm32h7x
  13 }
  14
  15 set _ENDIAN little
  16
  17 # Work-area is a space in RAM used for flash programming
  18 # By default use 64kB
  19 if { [info exists WORKAREASIZE] } {
  20    set _WORKAREASIZE $WORKAREASIZE
  21 } else {
  22    set _WORKAREASIZE 0x10000
  23 }
  24
  25 #jtag scan chain
  26 if { [info exists CPUTAPID] } {
  27    set _CPUTAPID $CPUTAPID
  28 } else {
  29    if { [using_jtag] } {
  30           set _CPUTAPID 0x6ba00477
  31    } {
  32       set _CPUTAPID 0x6ba02477
  33    }
  34 }
  35
  36 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  37
  38 if {[using_jtag]} {
  39  swj_newdap $_CHIPNAME bs -irlen 5
  40 }
  41
  42 set _TARGETNAME $_CHIPNAME.cpu
  43 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  44
  45 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  46
  47 set _FLASHNAME $_CHIPNAME.flash
  48 flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_TARGETNAME
  49
  50 # Clock after reset is HSI at 64 MHz, no need of PLL
  51 adapter_khz 1800
  52
  53 adapter_nsrst_delay 100
  54 if {[using_jtag]} {
  55  jtag_ntrst_delay 100
  56 }
  57
  58 # use hardware reset, connect under reset
  59 reset_config srst_only srst_nogate
  60
  61 if {![using_hla]} {
  62    # if srst is not fitted use SYSRESETREQ to
  63    # perform a soft reset
  64    cortex_m reset_config sysresetreq
  65 }
  66
  67 $_TARGETNAME configure -event examine-end {
  68         # Enable D3 and D1 DBG clocks
  69         # DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
  70         mmw 0x5C001004 0x00600000 0
  71
  72         # Enable debug during low power modes (uses more power)
  73         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3 & D1 Domains
  74         mmw 0x5C001004 0x00000187 0
  75
  76         # Stop watchdog counters during halt
  77         # DBGMCU_APB3FZ1 |= WWDG1
  78         mmw 0x5C001034 0x00000040 0
  79         # DBGMCU_APB4FZ1 |= WDGLSD1
  80         mmw 0x5C001054 0x00040000 0
  81 }
  82
  83 $_TARGETNAME configure -event trace-config {
  84         # Set TRACECLKEN; TRACE_MODE is set to async; when using sync
  85         # change this value accordingly to configure trace pins
  86         # assignment
  87         mmw 0x5C001004 0x00100000 0
  88 }
  89
  90 $_TARGETNAME configure -event reset-init {
  91         # Clock after reset is HSI at 64 MHz, no need of PLL
  92         adapter_khz 4000
  93 }