4 # stm32 devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
8 if { [info exists CHIPNAME] } {
9 set _CHIPNAME $CHIPNAME
14 if { [info exists ENDIAN] } {
20 # Work-area is a space in RAM used for flash programming
22 if { [info exists WORKAREASIZE] } {
23 set _WORKAREASIZE $WORKAREASIZE
25 set _WORKAREASIZE 0x2800
28 # JTAG speed should be <= F_CPU/6.
29 # F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
32 adapter_nsrst_delay 100
38 if { [info exists CPUTAPID] } {
39 set _CPUTAPID $CPUTAPID
42 # See STM Document RM0038
44 set _CPUTAPID 0x4ba00477
46 set _CPUTAPID1 0x2ba01477
47 set _CPUTAPID2 0x0bc11477
51 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID1 -expected-id $_CPUTAPID2
53 if { [info exists BSTAPID] } {
54 # FIXME this never gets used to override defaults...
57 # See STM Document RM0038
59 set _BSTAPID 0x06416041
63 swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
66 set _TARGETNAME $_CHIPNAME.cpu
67 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
69 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
71 # flash size will be probed
72 set _FLASHNAME $_CHIPNAME.flash
73 flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
76 # if srst is not fitted use SYSRESETREQ to
77 # perform a soft reset
78 cortex_m reset_config sysresetreq
81 proc stm32l_enable_HSI {} {
82 # Enable HSI as clock source
83 echo "STM32L: Enabling HSI"
86 mww 0x40023800 0x00000101
89 mww 0x40023808 0x00000001
95 $_TARGETNAME configure -event reset-init {
99 $_TARGETNAME configure -event reset-start {
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