tcl/target/stm32l1.cfg

   1 #
   2 # stm32l1 devices support both JTAG and SWD transports.
   3 #
   4
   5 source [find target/swj-dp.tcl]
   6
   7 if { [info exists CHIPNAME] } {
   8    set _CHIPNAME $CHIPNAME
   9 } else {
  10    set _CHIPNAME stm32l1
  11 }
  12
  13 set _ENDIAN little
  14
  15 # Work-area is a space in RAM used for flash programming
  16 # By default use 10kB
  17 if { [info exists WORKAREASIZE] } {
  18    set _WORKAREASIZE $WORKAREASIZE
  19 } else {
  20    set _WORKAREASIZE 0x2800
  21 }
  22
  23 # JTAG speed should be <= F_CPU/6.
  24 # F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
  25 adapter_khz 300
  26
  27 adapter_nsrst_delay 100
  28 if {[using_jtag]} {
  29  jtag_ntrst_delay 100
  30 }
  31
  32 #jtag scan chain
  33 if { [info exists CPUTAPID] } {
  34    set _CPUTAPID $CPUTAPID
  35 } else {
  36    if { [using_jtag] } {
  37       # See STM Document RM0038
  38       # Section 30.6.3 - corresponds to Cortex-M3 r2p0
  39       set _CPUTAPID 0x4ba00477
  40    } else {
  41       # SWD IDCODE (single drop, arm)
  42       set _CPUTAPID 0x2ba01477
  43    }
  44 }
  45
  46 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  47
  48 if { [info exists BSTAPID] } {
  49    # FIXME this never gets used to override defaults...
  50    set _BSTAPID $BSTAPID
  51 } else {
  52    # See STM Document RM0038 Section 30.6.1 Rev. 12
  53
  54    # Low and medium density
  55    set _BSTAPID1 0x06416041
  56    # Cat.2 device (medium+ density)
  57    set _BSTAPID2 0x06429041
  58    # Cat.3 device (medium+ density)
  59    set _BSTAPID3 0x06427041
  60    # Cat.4 device, STM32L15/6xxD or Cat.3 device, some STM32L15/6xxC-A models
  61    set _BSTAPID4 0x06436041
  62    # Cat.5 device (high density), STM32L15/6xxE
  63    set _BSTAPID5 0x06437041
  64 }
  65
  66 if {[using_jtag]} {
  67    swj_newdap $_CHIPNAME bs -irlen 5 \
  68    -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 expected-id $_BSTAPID3 \
  69    -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
  70 }
  71
  72 set _TARGETNAME $_CHIPNAME.cpu
  73 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  74
  75 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  76
  77 # flash size will be probed
  78 set _FLASHNAME $_CHIPNAME.flash
  79 flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
  80
  81 reset_config srst_nogate
  82
  83 if {![using_hla]} {
  84    # if srst is not fitted use SYSRESETREQ to
  85    # perform a soft reset
  86    cortex_m reset_config sysresetreq
  87 }
  88
  89 proc stm32l_enable_HSI {} {
  90         # Enable HSI as clock source
  91         echo "STM32L: Enabling HSI"
  92
  93         # Set HSION in RCC_CR
  94         mww 0x40023800 0x00000101
  95
  96         # Set HSI as SYSCLK
  97         mww 0x40023808 0x00000001
  98
  99         # Increase JTAG speed
 100         adapter_khz 2000
 101 }
 102
 103 $_TARGETNAME configure -event reset-init {
 104         stm32l_enable_HSI
 105 }
 106
 107 $_TARGETNAME configure -event reset-start {
 108         adapter_khz 300
 109 }