tcl/target/stm32l1.cfg

   1 #
   2 # stm32l1 devices support both JTAG and SWD transports.
   3 #
   4
   5 source [find target/swj-dp.tcl]
   6
   7 if { [info exists CHIPNAME] } {
   8    set _CHIPNAME $CHIPNAME
   9 } else {
  10    set _CHIPNAME stm32l
  11 }
  12
  13 if { [info exists ENDIAN] } {
  14    set _ENDIAN $ENDIAN
  15 } else {
  16    set _ENDIAN little
  17 }
  18
  19 # Work-area is a space in RAM used for flash programming
  20 # By default use 10kB
  21 if { [info exists WORKAREASIZE] } {
  22    set _WORKAREASIZE $WORKAREASIZE
  23 } else {
  24    set _WORKAREASIZE 0x2800
  25 }
  26
  27 # JTAG speed should be <= F_CPU/6.
  28 # F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
  29 adapter_khz 300
  30
  31 adapter_nsrst_delay 100
  32 if {[using_jtag]} {
  33  jtag_ntrst_delay 100
  34 }
  35
  36 #jtag scan chain
  37 if { [info exists CPUTAPID] } {
  38    set _CPUTAPID $CPUTAPID
  39 } else {
  40    if { [using_jtag] } {
  41       # See STM Document RM0038
  42       # Section 30.6.3 - corresponds to Cortex-M3 r2p0
  43       set _CPUTAPID 0x4ba00477
  44    } else {
  45       # SWD IDCODE (single drop, arm)
  46       set _CPUTAPID 0x2ba01477
  47    }
  48 }
  49
  50 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  51
  52 if { [info exists BSTAPID] } {
  53    # FIXME this never gets used to override defaults...
  54    set _BSTAPID $BSTAPID
  55 } else {
  56    # See STM Document RM0038 Section 30.6.1
  57    # (section 30.6.2 seems incorrect, at least in RM0038 DocID 15965 Rev 10)
  58
  59    # Low and medium density
  60    set _BSTAPID1 0x06416041
  61    # Cat.3 device (medium+ density)
  62    set _BSTAPID2 0x06427041
  63    # Cat.4 device, STM32L15/6xxD or Cat.3 device, some STM32L15/6xxC-A models
  64    set _BSTAPID3 0x06436041
  65    # Cat.5 device (high density), STM32L15/6xxE
  66    set _BSTAPID4 0x06437041
  67 }
  68
  69 if {[using_jtag]} {
  70    swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 -expected-id $_BSTAPID4
  71 }
  72
  73 set _TARGETNAME $_CHIPNAME.cpu
  74 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  75
  76 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  77
  78 # flash size will be probed
  79 set _FLASHNAME $_CHIPNAME.flash
  80 flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
  81
  82 if {![using_hla]} {
  83    # if srst is not fitted use SYSRESETREQ to
  84    # perform a soft reset
  85    cortex_m reset_config sysresetreq
  86 }
  87
  88 proc stm32l_enable_HSI {} {
  89         # Enable HSI as clock source
  90         echo "STM32L: Enabling HSI"
  91
  92         # Set HSION in RCC_CR
  93         mww 0x40023800 0x00000101
  94
  95         # Set HSI as SYSCLK
  96         mww 0x40023808 0x00000001
  97
  98         # Increase JTAG speed
  99         adapter_khz 2000
 100 }
 101
 102 $_TARGETNAME configure -event reset-init {
 103         stm32l_enable_HSI
 104 }
 105
 106 $_TARGETNAME configure -event reset-start {
 107         adapter_khz 300
 108 }