tcl/target/stm32l1.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #
   4 # stm32l1 devices support both JTAG and SWD transports.
   5 #
   6
   7 source [find target/swj-dp.tcl]
   8 source [find mem_helper.tcl]
   9
  10 if { [info exists CHIPNAME] } {
  11    set _CHIPNAME $CHIPNAME
  12 } else {
  13    set _CHIPNAME stm32l1
  14 }
  15
  16 set _ENDIAN little
  17
  18 # Work-area is a space in RAM used for flash programming
  19 # By default use 10kB
  20 if { [info exists WORKAREASIZE] } {
  21    set _WORKAREASIZE $WORKAREASIZE
  22 } else {
  23    set _WORKAREASIZE 0x2800
  24 }
  25
  26 # JTAG speed should be <= F_CPU/6.
  27 # F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
  28 adapter speed 300
  29
  30 adapter srst delay 100
  31 if {[using_jtag]} {
  32  jtag_ntrst_delay 100
  33 }
  34
  35 #jtag scan chain
  36 if { [info exists CPUTAPID] } {
  37    set _CPUTAPID $CPUTAPID
  38 } else {
  39    if { [using_jtag] } {
  40       # See STM Document RM0038
  41       # Section 30.6.3 - corresponds to Cortex-M3 r2p0
  42       set _CPUTAPID 0x4ba00477
  43    } else {
  44       # SWD IDCODE (single drop, arm)
  45       set _CPUTAPID 0x2ba01477
  46    }
  47 }
  48
  49 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  50 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  51
  52 if {[using_jtag]} {
  53    jtag newtap $_CHIPNAME bs -irlen 5
  54 }
  55
  56 set _TARGETNAME $_CHIPNAME.cpu
  57 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  58
  59 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  60
  61 # flash size will be probed
  62 set _FLASHNAME $_CHIPNAME.flash
  63 flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
  64
  65 reset_config srst_nogate
  66
  67 if {![using_hla]} {
  68    # if srst is not fitted use SYSRESETREQ to
  69    # perform a soft reset
  70    cortex_m reset_config sysresetreq
  71 }
  72
  73 proc stm32l_enable_HSI {} {
  74         # Enable HSI as clock source
  75         echo "STM32L: Enabling HSI"
  76
  77         # Set HSION in RCC_CR
  78         mmw 0x40023800 0x00000101 0
  79
  80         # Set HSI as SYSCLK
  81         mmw 0x40023808 0x00000001 0
  82
  83         # Increase JTAG speed
  84         adapter speed 2000
  85 }
  86
  87 $_TARGETNAME configure -event reset-init {
  88         stm32l_enable_HSI
  89 }
  90
  91 $_TARGETNAME configure -event reset-start {
  92         adapter speed 300
  93 }
  94
  95 $_TARGETNAME configure -event examine-end {
  96         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  97         mmw 0xE0042004 0x00000007 0
  98
  99         # Stop watchdog counters during halt
 100         # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
 101         mmw 0xE0042008 0x00001800 0
 102 }
 103
 104 $_TARGETNAME configure -event trace-config {
 105         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
 106         # change this value accordingly to configure trace pins
 107         # assignment
 108         mmw 0xE0042004 0x00000020 0
 109 }