tcl/target/stm32l1.cfg

   1 #
   2 # stm32l1 devices support both JTAG and SWD transports.
   3 #
   4
   5 source [find target/swj-dp.tcl]
   6 source [find mem_helper.tcl]
   7
   8 if { [info exists CHIPNAME] } {
   9    set _CHIPNAME $CHIPNAME
  10 } else {
  11    set _CHIPNAME stm32l1
  12 }
  13
  14 set _ENDIAN little
  15
  16 # Work-area is a space in RAM used for flash programming
  17 # By default use 10kB
  18 if { [info exists WORKAREASIZE] } {
  19    set _WORKAREASIZE $WORKAREASIZE
  20 } else {
  21    set _WORKAREASIZE 0x2800
  22 }
  23
  24 # JTAG speed should be <= F_CPU/6.
  25 # F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
  26 adapter speed 300
  27
  28 adapter srst delay 100
  29 if {[using_jtag]} {
  30  jtag_ntrst_delay 100
  31 }
  32
  33 #jtag scan chain
  34 if { [info exists CPUTAPID] } {
  35    set _CPUTAPID $CPUTAPID
  36 } else {
  37    if { [using_jtag] } {
  38       # See STM Document RM0038
  39       # Section 30.6.3 - corresponds to Cortex-M3 r2p0
  40       set _CPUTAPID 0x4ba00477
  41    } else {
  42       # SWD IDCODE (single drop, arm)
  43       set _CPUTAPID 0x2ba01477
  44    }
  45 }
  46
  47 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  48 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  49
  50 if {[using_jtag]} {
  51    jtag newtap $_CHIPNAME bs -irlen 5
  52 }
  53
  54 set _TARGETNAME $_CHIPNAME.cpu
  55 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  56
  57 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  58
  59 # flash size will be probed
  60 set _FLASHNAME $_CHIPNAME.flash
  61 flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
  62
  63 reset_config srst_nogate
  64
  65 if {![using_hla]} {
  66    # if srst is not fitted use SYSRESETREQ to
  67    # perform a soft reset
  68    cortex_m reset_config sysresetreq
  69 }
  70
  71 proc stm32l_enable_HSI {} {
  72         # Enable HSI as clock source
  73         echo "STM32L: Enabling HSI"
  74
  75         # Set HSION in RCC_CR
  76         mmw 0x40023800 0x00000101 0
  77
  78         # Set HSI as SYSCLK
  79         mmw 0x40023808 0x00000001 0
  80
  81         # Increase JTAG speed
  82         adapter speed 2000
  83 }
  84
  85 $_TARGETNAME configure -event reset-init {
  86         stm32l_enable_HSI
  87 }
  88
  89 $_TARGETNAME configure -event reset-start {
  90         adapter speed 300
  91 }
  92
  93 $_TARGETNAME configure -event examine-end {
  94         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  95         mmw 0xE0042004 0x00000007 0
  96
  97         # Stop watchdog counters during halt
  98         # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
  99         mmw 0xE0042008 0x00001800 0
 100 }
 101
 102 $_TARGETNAME configure -event trace-config {
 103         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
 104         # change this value accordingly to configure trace pins
 105         # assignment
 106         mmw 0xE0042004 0x00000020 0
 107 }