tcl/target/stm32l1.cfg

   1 #
   2 # stm32l1 devices support both JTAG and SWD transports.
   3 #
   4
   5 source [find target/swj-dp.tcl]
   6 source [find mem_helper.tcl]
   7
   8 if { [info exists CHIPNAME] } {
   9    set _CHIPNAME $CHIPNAME
  10 } else {
  11    set _CHIPNAME stm32l1
  12 }
  13
  14 set _ENDIAN little
  15
  16 # Work-area is a space in RAM used for flash programming
  17 # By default use 10kB
  18 if { [info exists WORKAREASIZE] } {
  19    set _WORKAREASIZE $WORKAREASIZE
  20 } else {
  21    set _WORKAREASIZE 0x2800
  22 }
  23
  24 # JTAG speed should be <= F_CPU/6.
  25 # F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
  26 adapter_khz 300
  27
  28 adapter_nsrst_delay 100
  29 if {[using_jtag]} {
  30  jtag_ntrst_delay 100
  31 }
  32
  33 #jtag scan chain
  34 if { [info exists CPUTAPID] } {
  35    set _CPUTAPID $CPUTAPID
  36 } else {
  37    if { [using_jtag] } {
  38       # See STM Document RM0038
  39       # Section 30.6.3 - corresponds to Cortex-M3 r2p0
  40       set _CPUTAPID 0x4ba00477
  41    } else {
  42       # SWD IDCODE (single drop, arm)
  43       set _CPUTAPID 0x2ba01477
  44    }
  45 }
  46
  47 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  48
  49 if {[using_jtag]} {
  50    jtag newtap $_CHIPNAME bs -irlen 5
  51 }
  52
  53 set _TARGETNAME $_CHIPNAME.cpu
  54 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  55
  56 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  57
  58 # flash size will be probed
  59 set _FLASHNAME $_CHIPNAME.flash
  60 flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
  61
  62 reset_config srst_nogate
  63
  64 if {![using_hla]} {
  65    # if srst is not fitted use SYSRESETREQ to
  66    # perform a soft reset
  67    cortex_m reset_config sysresetreq
  68 }
  69
  70 proc stm32l_enable_HSI {} {
  71         # Enable HSI as clock source
  72         echo "STM32L: Enabling HSI"
  73
  74         # Set HSION in RCC_CR
  75         mww 0x40023800 0x00000101
  76
  77         # Set HSI as SYSCLK
  78         mww 0x40023808 0x00000001
  79
  80         # Increase JTAG speed
  81         adapter_khz 2000
  82 }
  83
  84 $_TARGETNAME configure -event reset-init {
  85         stm32l_enable_HSI
  86 }
  87
  88 $_TARGETNAME configure -event reset-start {
  89         adapter_khz 300
  90 }
  91
  92 $_TARGETNAME configure -event examine-end {
  93         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  94         mmw 0xE0042004 0x00000007 0
  95
  96         # Stop watchdog counters during halt
  97         # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
  98         mmw 0xE0042008 0x00001800 0
  99 }
 100
 101 $_TARGETNAME configure -event trace-config {
 102         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
 103         # change this value accordingly to configure trace pins
 104         # assignment
 105         mmw 0xE0042004 0x00000020 0
 106 }