tcl/target/stm32l4x.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # script for stm32l4x family
   4
   5 #
   6 # stm32l4 devices support both JTAG and SWD transports.
   7 #
   8 source [find target/swj-dp.tcl]
   9 source [find mem_helper.tcl]
  10
  11 if { [info exists CHIPNAME] } {
  12    set _CHIPNAME $CHIPNAME
  13 } else {
  14    set _CHIPNAME stm32l4x
  15 }
  16
  17 set _ENDIAN little
  18
  19 # Work-area is a space in RAM used for flash programming
  20 # By default use 40kB (Available RAM in smallest device STM32L412)
  21 if { [info exists WORKAREASIZE] } {
  22    set _WORKAREASIZE $WORKAREASIZE
  23 } else {
  24    set _WORKAREASIZE 0xa000
  25 }
  26
  27 #jtag scan chain
  28 if { [info exists CPUTAPID] } {
  29    set _CPUTAPID $CPUTAPID
  30 } else {
  31    if { [using_jtag] } {
  32       # See STM Document RM0351
  33       # Section 44.6.3 - corresponds to Cortex-M4 r0p1
  34       set _CPUTAPID 0x4ba00477
  35    } {
  36       set _CPUTAPID 0x2ba01477
  37    }
  38 }
  39
  40 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  41 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  42
  43 tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
  44
  45 if {[using_jtag]} {
  46    jtag newtap $_CHIPNAME bs -irlen 5
  47 }
  48
  49 set _TARGETNAME $_CHIPNAME.cpu
  50 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  51
  52 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  53
  54 set _FLASHNAME $_CHIPNAME.flash
  55 flash bank $_FLASHNAME stm32l4x 0x08000000 0 0 0 $_TARGETNAME
  56 flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
  57
  58 if { [info exists QUADSPI] && $QUADSPI } {
  59    set a [llength [flash list]]
  60    set _QSPINAME $_CHIPNAME.qspi
  61    flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
  62 } else {
  63    if { [info exists OCTOSPI1] && $OCTOSPI1 } {
  64       set a [llength [flash list]]
  65       set _OCTOSPINAME1 $_CHIPNAME.octospi1
  66       flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
  67    }
  68    if { [info exists OCTOSPI2] && $OCTOSPI2 } {
  69       set b [llength [flash list]]
  70       set _OCTOSPINAME2 $_CHIPNAME.octospi2
  71       flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_TARGETNAME 0xA0001400
  72    }
  73 }
  74
  75 # Common knowledges tells JTAG speed should be <= F_CPU/6.
  76 # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
  77 # the safe side.
  78 #
  79 # Note that there is a pretty wide band where things are
  80 # more or less stable, see http://openocd.zylin.com/#/c/3366/
  81 adapter speed 500
  82
  83 adapter srst delay 100
  84 if {[using_jtag]} {
  85  jtag_ntrst_delay 100
  86 }
  87
  88 reset_config srst_nogate
  89
  90 if {![using_hla]} {
  91    # if srst is not fitted use SYSRESETREQ to
  92    # perform a soft reset
  93    cortex_m reset_config sysresetreq
  94 }
  95
  96 $_TARGETNAME configure -event examine-end {
  97         # Enable debug during low power modes (uses more power)
  98         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  99         mmw 0xE0042004 0x00000007 0
 100
 101         # Stop watchdog counters during halt
 102         # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
 103         mmw 0xE0042008 0x00001800 0
 104 }
 105
 106 proc proc_post_enable {_chipname} {
 107         targets $_chipname.cpu
 108
 109         if { [$_chipname.tpiu cget -protocol] eq "sync" } {
 110                 switch [$_chipname.tpiu cget -port-width] {
 111                         1 {
 112                                 mmw 0xE0042004 0x00000060 0x000000c0
 113                                 mmw 0x48001020 0x00000000 0x0000ff00
 114                                 mmw 0x48001000 0x000000a0 0x000000f0
 115                                 mmw 0x48001008 0x000000f0 0x00000000
 116                           }
 117                         2 {
 118                                 mmw 0xE0042004 0x000000a0 0x000000c0
 119                                 mmw 0x48001020 0x00000000 0x000fff00
 120                                 mmw 0x48001000 0x000002a0 0x000003f0
 121                                 mmw 0x48001008 0x000003f0 0x00000000
 122                           }
 123                         4 {
 124                                 mmw 0xE0042004 0x000000e0 0x000000c0
 125                                 mmw 0x48001020 0x00000000 0x0fffff00
 126                                 mmw 0x48001000 0x00002aa0 0x00003ff0
 127                                 mmw 0x48001008 0x00003ff0 0x00000000
 128                           }
 129                 }
 130         } else {
 131                 mmw 0xE0042004 0x00000020 0x000000c0
 132         }
 133 }
 134
 135 $_CHIPNAME.tpiu configure -event post-enable "proc_post_enable $_CHIPNAME"
 136
 137 $_TARGETNAME configure -event reset-init {
 138         # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
 139         # Use MSI 24 MHz clock, compliant even with VOS == 2.
 140         # 3 WS compliant with VOS == 2 and 24 MHz.
 141         mww 0x40022000 0x00000103   ;# FLASH_ACR = PRFTBE | 3(Latency)
 142         mww 0x40021000 0x00000099   ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9
 143
 144         # Boost JTAG frequency
 145         adapter speed 4000
 146 }
 147
 148 $_TARGETNAME configure -event reset-start {
 149         # Reset clock is MSI (4 MHz)
 150         adapter speed 500
 151 }