tcl/target/stm32l4x.cfg

   1 # script for stm32l4x family
   2
   3 #
   4 # stm32l4 devices support both JTAG and SWD transports.
   5 #
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10    set _CHIPNAME $CHIPNAME
  11 } else {
  12    set _CHIPNAME stm32l4x
  13 }
  14
  15 set _ENDIAN little
  16
  17 # Work-area is a space in RAM used for flash programming
  18 # Smallest current target has 64kB ram, use 32kB by default to avoid surprises
  19 if { [info exists WORKAREASIZE] } {
  20    set _WORKAREASIZE $WORKAREASIZE
  21 } else {
  22    set _WORKAREASIZE 0x8000
  23 }
  24
  25 #jtag scan chain
  26 if { [info exists CPUTAPID] } {
  27    set _CPUTAPID $CPUTAPID
  28 } else {
  29    if { [using_jtag] } {
  30       # See STM Document RM0351
  31       # Section 44.6.3 - corresponds to Cortex-M4 r0p1
  32       set _CPUTAPID 0x4ba00477
  33    } {
  34       set _CPUTAPID 0x2ba01477
  35    }
  36 }
  37
  38 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  39
  40 if { [info exists BSTAPID] } {
  41    set _BSTAPID $BSTAPID
  42 } else {
  43   # See STM Document RM0351
  44   # Section 44.6.3
  45   # STM32L4X6
  46   set _BSTAPID1 0x06415041
  47 }
  48
  49 if {[using_jtag]} {
  50  swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1
  51 }
  52
  53 set _TARGETNAME $_CHIPNAME.cpu
  54 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  55
  56 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  57
  58 set _FLASHNAME $_CHIPNAME.flash
  59 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
  60
  61 # Common knowledges tells JTAG speed should be <= F_CPU/6.
  62 # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
  63 # the safe side.
  64 #
  65 # Note that there is a pretty wide band where things are
  66 # more or less stable, see http://openocd.zylin.com/#/c/3366/
  67 adapter_khz 500
  68
  69 adapter_nsrst_delay 100
  70 if {[using_jtag]} {
  71  jtag_ntrst_delay 100
  72 }
  73
  74 reset_config srst_nogate
  75
  76 if {![using_hla]} {
  77    # if srst is not fitted use SYSRESETREQ to
  78    # perform a soft reset
  79    cortex_m reset_config sysresetreq
  80 }
  81
  82 $_TARGETNAME configure -event reset-init {
  83         # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
  84         # Use MSI 24 MHz clock, compliant even with VOS == 2.
  85         # 3 WS compliant with VOS == 2 and 24 MHz.
  86         mww 0x40022000 0x00000103   ;# FLASH_ACR = PRFTBE | 3(Latency)
  87         mww 0x40021000 0x00000099   ;# RCC_CR = MSI_ON | MSIRGSEL| MSI Range 10
  88         # Boost JTAG frequency
  89         adapter_khz 4000
  90 }
  91
  92 $_TARGETNAME configure -event reset-start {
  93         # Reset clock is MSI (4 MHz)
  94         adapter_khz 500
  95 }
  96
  97 $_TARGETNAME configure -event examine-end {
  98         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  99         mmw 0xE0042004 0x00000007 0
 100
 101         # Stop watchdog counters during halt
 102         # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
 103         mmw 0xE0042008 0x00001800 0
 104 }
 105
 106 $_TARGETNAME configure -event trace-config {
 107         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
 108         # change this value accordingly to configure trace pins
 109         # assignment
 110         mmw 0xE0042004 0x00000020 0
 111 }