tcl/target/stm32l5x.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # script for stm32l5x family
   4
   5 #
   6 # stm32l5 devices support both JTAG and SWD transports.
   7 #
   8 source [find target/swj-dp.tcl]
   9 source [find mem_helper.tcl]
  10
  11 if { [info exists CHIPNAME] } {
  12         set _CHIPNAME $CHIPNAME
  13 } else {
  14         set _CHIPNAME stm32l5x
  15 }
  16
  17 set _ENDIAN little
  18
  19 # Work-area is a space in RAM used for flash programming
  20 # By default use 64kB
  21 if { [info exists WORKAREASIZE] } {
  22         set _WORKAREASIZE $WORKAREASIZE
  23 } else {
  24         set _WORKAREASIZE 0x10000
  25 }
  26
  27 #jtag scan chain
  28 if { [info exists CPUTAPID] } {
  29         set _CPUTAPID $CPUTAPID
  30 } else {
  31         if { [using_jtag] } {
  32                 # See STM Document RM0438
  33                 # RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers
  34                 # Corresponds to Cortex®-M33 JTAG debug port ID code
  35                 set _CPUTAPID 0x0ba04477
  36         } {
  37                 # SWD IDCODE (single drop, arm)
  38                 set _CPUTAPID 0x0be12477
  39         }
  40 }
  41
  42 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  43 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  44
  45 if {[using_jtag]} {
  46         jtag newtap $_CHIPNAME bs -irlen 5
  47 }
  48
  49 set _TARGETNAME $_CHIPNAME.cpu
  50 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  51
  52 # use non-secure RAM by default
  53 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  54
  55 # create sec/ns flash and otp memories (sizes will be probed)
  56 flash bank $_CHIPNAME.flash_ns      stm32l4x 0x08000000 0 0 0 $_TARGETNAME
  57 flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME
  58 flash bank $_CHIPNAME.otp           stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
  59
  60 # Common knowledges tells JTAG speed should be <= F_CPU/6.
  61 # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
  62 # the safe side.
  63 #
  64 # Note that there is a pretty wide band where things are
  65 # more or less stable, see http://openocd.zylin.com/#/c/3366/
  66 adapter speed 500
  67
  68 adapter srst delay 100
  69 if {[using_jtag]} {
  70         jtag_ntrst_delay 100
  71 }
  72
  73 reset_config srst_nogate
  74
  75 if {![using_hla]} {
  76         # if srst is not fitted use SYSRESETREQ to
  77         # perform a soft reset
  78         cortex_m reset_config sysresetreq
  79 }
  80
  81 proc is_secure {} {
  82         # read Debug Security Control and Status Regsiter (DSCSR) and check CDS (bit 16)
  83         set DSCSR [mrw 0xE000EE08]
  84         return [expr {($DSCSR & (1 << 16)) != 0}]
  85 }
  86
  87 proc clock_config_110_mhz {} {
  88         set offset [expr {[is_secure] ? 0x10000000 : 0}]
  89         # MCU clock is MSI (4MHz) after reset, set MCU freq at 110 MHz with PLL
  90         # RCC_APB1ENR1 = PWREN
  91         mww [expr {0x40021058 + $offset}] 0x10000000
  92         # delay for register clock enable (read back reg)
  93         mrw [expr {0x40021058 + $offset}]
  94         # PWR_CR1 : VOS Range 0
  95         mww [expr {0x40007000 + $offset}] 0
  96         # while (PWR_SR2 & VOSF)
  97         while {([mrw [expr {0x40007014 + $offset}]] & 0x0400)} {}
  98         # FLASH_ACR : 5 WS for 110 MHz HCLK
  99         mww 0x40022000 0x00000005
 100         # RCC_PLLCFGR = PLLP=PLLQ=0, PLLR=00=2, PLLREN=1, PLLN=55, PLLM=0000=1, PLLSRC=MSI 4MHz
 101         # fVCO = 4 x 55 /1 = 220
 102         # SYSCLOCK = fVCO/PLLR = 220/2 = 110 MHz
 103         mww [expr {0x4002100C + $offset}] 0x01003711
 104         # RCC_CR |= PLLON
 105         mmw [expr {0x40021000 + $offset}] 0x01000000 0
 106         # while !(RCC_CR & PLLRDY)
 107         while {!([mrw [expr {0x40021000 + $offset}]] & 0x02000000)} {}
 108         # RCC_CFGR |= SW_PLL
 109         mmw [expr {0x40021008 + $offset}] 0x00000003 0
 110         # while ((RCC_CFGR & SWS) != PLL)
 111         while {([mrw [expr {0x40021008 + $offset}]] & 0x0C) != 0x0C} {}
 112 }
 113
 114 proc ahb_ap_non_secure_access {} {
 115         # SPROT=1=Non Secure access, Priv=1
 116         [[target current] cget -dap] apcsw 0x4B000000 0x4F000000
 117 }
 118
 119 proc ahb_ap_secure_access {} {
 120         # SPROT=0=Secure access, Priv=1
 121         [[target current] cget -dap] apcsw 0x0B000000 0x4F000000
 122 }
 123
 124 $_TARGETNAME configure -event reset-init {
 125         clock_config_110_mhz
 126         # Boost JTAG frequency
 127         adapter speed 4000
 128 }
 129
 130 $_TARGETNAME configure -event reset-start {
 131         # Reset clock is MSI (4 MHz)
 132         adapter speed 480
 133 }
 134
 135 $_TARGETNAME configure -event examine-end {
 136         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP
 137         mmw 0xE0044004 0x00000006 0
 138
 139         # Stop watchdog counters during halt
 140         # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
 141         mmw 0xE0044008 0x00001800 0
 142 }
 143
 144 $_TARGETNAME configure -event halted {
 145         set secure [is_secure]
 146
 147         if {$secure} {
 148                 set secure_str "Secure"
 149                 ahb_ap_secure_access
 150         } else {
 151                 set secure_str "Non-Secure"
 152                 ahb_ap_non_secure_access
 153         }
 154
 155         # print the secure state only when it changes
 156         set _TARGETNAME [target current]
 157         global $_TARGETNAME.secure
 158
 159         if {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} {
 160                 echo "CPU in $secure_str state"
 161                 # update saved security state
 162                 set $_TARGETNAME.secure $secure
 163         }
 164 }
 165
 166 $_TARGETNAME configure -event gdb-flash-erase-start {
 167         set use_secure_workarea 0
 168         # check if FLASH_OPTR.TZEN is enabled
 169         set FLASH_OPTR [mrw 0x40022040]
 170         if {[expr {$FLASH_OPTR & 0x80000000}] == 0} {
 171                 echo "TZEN option bit disabled"
 172                 ahb_ap_non_secure_access
 173         } {
 174                 ahb_ap_secure_access
 175                 echo "TZEN option bit enabled"
 176
 177                 # check if FLASH_OPTR.RDP is not Level 0.5
 178                 if {[expr {$FLASH_OPTR & 0xFF}] != 0x55} {
 179                         set use_secure_workarea 1
 180                 }
 181         }
 182
 183         set workarea_addr [$_TARGETNAME cget -work-area-phys]
 184         echo "workarea_addr $workarea_addr"
 185
 186         if {$use_secure_workarea} {
 187                 set workarea_addr [expr {$workarea_addr | 0x10000000}]
 188         } {
 189                 set workarea_addr [expr {$workarea_addr & ~0x10000000}]
 190         }
 191
 192         $_TARGETNAME configure -work-area-phys $workarea_addr
 193 }
 194
 195 $_TARGETNAME configure -event trace-config {
 196         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
 197         # change this value accordingly to configure trace pins
 198         # assignment
 199         mmw 0xE0044004 0x00000020 0
 200 }