1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # script for stm32l5x family
4 # stm32l5x devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
7 source [find mem_helper.tcl]
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
12 set _CHIPNAME stm32l5x
15 source [find target/stm32x5x_common.cfg]
17 proc stm32l5x_clock_config {} {
18 set offset [expr {[stm32x5x_is_secure] ? 0x10000000 : 0}]
19 # MCU clock is MSI (4MHz) after reset, set MCU freq at 110 MHz with PLL
20 # RCC_APB1ENR1 = PWREN
21 mww [expr {0x40021058 + $offset}] 0x10000000
22 # delay for register clock enable (read back reg)
23 mrw [expr {0x40021058 + $offset}]
24 # PWR_CR1 : VOS Range 0
25 mww [expr {0x40007000 + $offset}] 0
26 # while (PWR_SR2 & VOSF)
27 while {([mrw [expr {0x40007014 + $offset}]] & 0x0400)} {}
28 # FLASH_ACR : 5 WS for 110 MHz HCLK
29 mww 0x40022000 0x00000005
30 # RCC_PLLCFGR = PLLP=PLLQ=0, PLLR=00=2, PLLREN=1, PLLN=55, PLLM=0000=1, PLLSRC=MSI 4MHz
31 # fVCO = 4 x 55 /1 = 220
32 # SYSCLOCK = fVCO/PLLR = 220/2 = 110 MHz
33 mww [expr {0x4002100C + $offset}] 0x01003711
35 mmw [expr {0x40021000 + $offset}] 0x01000000 0
36 # while !(RCC_CR & PLLRDY)
37 while {!([mrw [expr {0x40021000 + $offset}]] & 0x02000000)} {}
39 mmw [expr {0x40021008 + $offset}] 0x00000003 0
40 # while ((RCC_CFGR & SWS) != PLL)
41 while {([mrw [expr {0x40021008 + $offset}]] & 0x0C) != 0x0C} {}
44 $_TARGETNAME configure -event reset-init {
46 # Boost JTAG frequency
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